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| Paper Abstract and Keywords | ||
| Presentation | 2024-07-22 16:05 Design of Low-Latency Block Ciphers with Multiple Linear Layers Kazuma Nakata, Tatsuya Ishikawa (Hyogo Uiv.), Kosei Sakamoto (Mitsubishi Electric), Kazuhiko Minematsu (NEC), Takanori Isobe (Hyogo Uiv.)  ISEC2024-22 SITE2024-19 BioX2024-32 HWS2024-22 ICSS2024-26 EMM2024-28 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Midori is a low-latency block cipher with an SPN (Substitution-Permutation Network) structure.At CSS 2023, a de- sign that uses multiple linear layers differing by rounds was presented, demonstrating better properties in terms of Active S-box evaluation―a measure of resistance to differential and linear attacks―compared to Midori. In low-latency implementations, it is common to use an unrolled implementation where all rounds are implemented, and the use of multiple cell permutations in this study incurs minimal implementation overhead in terms of latency and circuit size. In this study, by appropriately combining multiple linear layers and nonlinear layers, we propose a design that achieves better performance than Midori in terms of security against differential and linear attacks. Specifically, by considering combinations of multiple linear layers and three types of nonlinear layers that can be implemented with low latency, we demonstrate a design that guarantees higher security than Midori against differential and linear attacks in all rounds. In particular, for the most effective attack against Midori, the linear attack, we propose a design that can guarantee security with fewer rounds than Midori. Additionally, for two of the three types of nonlinear layers, which have higher latency performance than the S-box used in Midori128, the proposed design achieves both higher security and latency performance compared to Midori128. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low-latency block cipher / SAT solver / differential cryptanalysis / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 124, no. 120, ISEC2024-22, pp. 96-103, July 2024. | |
| Paper # | ISEC2024-22 | |
| Date of Issue | 2024-07-15 (ISEC, SITE, BioX, HWS, ICSS, EMM) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ISEC2024-22 SITE2024-19 BioX2024-32 HWS2024-22 ICSS2024-26 EMM2024-28 |
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| Conference Information | |
| Committee | EMM BioX ISEC SITE ICSS HWS IPSJ-CSEC IPSJ-SPT |
| Conference Date | 2024-07-22 - 2024-07-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Sapporo Convention Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ISEC |
| Conference Code | 2024-07-EMM-BioX-ISEC-SITE-ICSS-HWS-CSEC-SPT |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Low-Latency Block Ciphers with Multiple Linear Layers |
| Sub Title (in English) | |
| Keyword(1) | Low-latency block cipher |
| Keyword(2) | SAT solver |
| Keyword(3) | differential cryptanalysis |
| Keyword(4) | |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazuma Nakata |
| 1st Author's Affiliation | University of Hyogo (Hyogo Uiv.) |
| 2nd Author's Name | Tatsuya Ishikawa |
| 2nd Author's Affiliation | University of Hyogo (Hyogo Uiv.) |
| 3rd Author's Name | Kosei Sakamoto |
| 3rd Author's Affiliation | Mitsubishi Electric Corporation (Mitsubishi Electric) |
| 4th Author's Name | Kazuhiko Minematsu |
| 4th Author's Affiliation | NEC Corporation (NEC) |
| 5th Author's Name | Takanori Isobe |
| 5th Author's Affiliation | University of Hyogo (Hyogo Uiv.) |
| Speaker | Author-1 |
| Date Time | 2024-07-22 16:05:00 |
| Presentation Time | 25 minutes |
| Registration for | ISEC |
| Paper # | ISEC2024-22, SITE2024-19, BioX2024-32, HWS2024-22, ICSS2024-26, EMM2024-28 |
| Volume (vol) | vol.124 |
| Number (no) | no.120(ISEC), no.121(SITE), no.122(BioX), no.123(HWS), no.124(ICSS), no.125(EMM) |
| Page | pp.96-103 |
| #Pages | 8 |
| Date of Issue | 2024-07-15 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
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