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Paper Abstract and Keywords
Presentation 2024-07-22 14:50
Performance Evaluation of Improved SuperSonic Glitch PUF
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) ISEC2024-26 SITE2024-23 BioX2024-36 HWS2024-26 ICSS2024-30 EMM2024-32
Abstract (in Japanese) (See Japanese page) 
(in English) In accordance with the basic plan for science and technology in Japan, The fundamental technologies of digital social infrastructures and their cybersecurity countermeasures have become very important. For industrial hardware devices, it is essential not only to apply state-of-the-art cryptographic techniques but also to implement countermeasures against threats such as side-channel attacks and hardware trojans. Thus, We have proposed SuperSonic-GPUF, which is a combination of SuperSonic, a lightweight block cipher with low latency, and glitch PUF for device authentication. On the other hand, conventional SuperSonic-GPUF has some implementation issues, such as the need for a large error correction circuit due to insufficient stability of the authentication ID. Against this background, this study evaluates the authentication performance of SuperSonic-GPUF in detail and proposes an implementation method that can improve the authentication performance. The evaluation experiments in this study revealed that the optimal challenge signal for the SuperSonic-GPUF is the cryptographic intermediate value after in the second round function.
Keyword (in Japanese) (See Japanese page) 
(in English) hardware security / physically unclonable function / lightweight block cipher / SuperSonic / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 123, HWS2024-26, pp. 128-132, July 2024.
Paper # HWS2024-26 
Date of Issue 2024-07-15 (ISEC, SITE, BioX, HWS, ICSS, EMM) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ISEC2024-26 SITE2024-23 BioX2024-36 HWS2024-26 ICSS2024-30 EMM2024-32

Conference Information
Committee EMM BioX ISEC SITE ICSS HWS IPSJ-CSEC IPSJ-SPT 
Conference Date 2024-07-22 - 2024-07-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Sapporo Convention Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To HWS 
Conference Code 2024-07-EMM-BioX-ISEC-SITE-ICSS-HWS-CSEC-SPT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation of Improved SuperSonic Glitch PUF 
Sub Title (in English)  
Keyword(1) hardware security  
Keyword(2) physically unclonable function  
Keyword(3) lightweight block cipher  
Keyword(4) SuperSonic  
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1st Author's Name Shu Takemoto  
1st Author's Affiliation Meijo University (Meijo Univ.)
2nd Author's Name Yusuke Nozaki  
2nd Author's Affiliation Meijo University (Meijo Univ.)
3rd Author's Name Masaya Yoshikawa  
3rd Author's Affiliation Meijo University (Meijo Univ.)
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Speaker Author-1 
Date Time 2024-07-22 14:50:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # ISEC2024-26, SITE2024-23, BioX2024-36, HWS2024-26, ICSS2024-30, EMM2024-32 
Volume (vol) vol.124 
Number (no) no.120(ISEC), no.121(SITE), no.122(BioX), no.123(HWS), no.124(ICSS), no.125(EMM) 
Page pp.128-132 
#Pages 5 
Date of Issue 2024-07-15 (ISEC, SITE, BioX, HWS, ICSS, EMM) 

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