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Paper Abstract and Keywords
Presentation 2024-11-01 17:30
Secret Sharing Supporting Multi-input gates on FPGA Design for Less Communication Bandwidth Network
Yinfan Zhao, Makoto Ikeda (UTokyo) HWS2024-73 ICD2024-44
Abstract (in Japanese) (See Japanese page) 
(in English) Multi-Party Computation (MPC) is a cryptographic technology that enables multiple participants to collaboratively compute the value of a function without revealing their individual inputs. Secret sharing is one of the main technological approaches for implementing MPC. Although secret sharing is computationally lightweight, compared with other technological approaches, its core drawback is that it requires too many communication rounds in computation. This paper focuses on decreasing communication rounds and bandwidth of the secret sharing on hardware. Rather than simple instructions, complex instructions can reduce the number of communication rounds. Furthermore, we also have a good performance on computation. To verify our performance, the hardware design is implemented on the UltraScale+ VU13P FPGA. Compared to previous implementations of the reference works, our work is 53% faster.
Keyword (in Japanese) (See Japanese page) 
(in English) Secret Sharing / Multi-Party Computation / FPGA / Hardware Design / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 230, ICD2024-44, pp. 59-64, Nov. 2024.
Paper # ICD2024-44 
Date of Issue 2024-10-25 (HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF HWS2024-73 ICD2024-44

Conference Information
Committee HWS ICD  
Conference Date 2024-11-01 - 2024-11-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Hirosaki University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Hardware Security, etc. 
Paper Information
Registration To ICD 
Conference Code 2024-11-HWS-ICD 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Secret Sharing Supporting Multi-input gates on FPGA Design for Less Communication Bandwidth Network 
Sub Title (in English)  
Keyword(1) Secret Sharing  
Keyword(2) Multi-Party Computation  
Keyword(3) FPGA  
Keyword(4) Hardware Design  
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1st Author's Name Yinfan Zhao  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2024-11-01 17:30:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # HWS2024-73, ICD2024-44 
Volume (vol) vol.124 
Number (no) no.229(HWS), no.230(ICD) 
Page pp.59-64 
#Pages 6 
Date of Issue 2024-10-25 (HWS, ICD) 

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