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Paper Abstract and Keywords
Presentation 2024-11-01 17:05
Fixed Modulus Modular Reduction with Manipulated Lookup Table Method
Anawin Opasatian, Makoto Ikeda (Tokyo Univ.) HWS2024-72 ICD2024-43
Abstract (in Japanese) (See Japanese page) 
(in English) Modular reduction is vital to many cryptographic schemes. In cases where a fixed modulus is used, numerous algorithms have been developed to optimize modular reduction, including those designed for specific modulus families such as Generalized Mersenne or Crandall primes. In this work, we present an optimization to fixed modulus Lookup Table Modular Reduction, called Manipulated Lookup Table Modular Reduction. Our proposed method can devise efficient modular reduction for any modulus and, in certain cases, matches or exceeds the performance of previous special reduction algorithms. Our method offers superior circuit performance compared to state-of-the-art methods for multi-stage modular multipliers, improving the Latency/Area-Interleaved Time for SIKE434 and BLS12-381 modular multipliers by 62%/13% and 88%/29%, respectively.
Keyword (in Japanese) (See Japanese page) 
(in English) High-performance Digital Circuit / Modular Multiplier / Efficient Reduction / Lookup Table Modular Reduction / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 230, ICD2024-43, pp. 53-58, Nov. 2024.
Paper # ICD2024-43 
Date of Issue 2024-10-25 (HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF HWS2024-72 ICD2024-43

Conference Information
Committee HWS ICD  
Conference Date 2024-11-01 - 2024-11-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Hirosaki University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Hardware Security, etc. 
Paper Information
Registration To ICD 
Conference Code 2024-11-HWS-ICD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fixed Modulus Modular Reduction with Manipulated Lookup Table Method 
Sub Title (in English)  
Keyword(1) High-performance Digital Circuit  
Keyword(2) Modular Multiplier  
Keyword(3) Efficient Reduction  
Keyword(4) Lookup Table Modular Reduction  
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1st Author's Name Anawin Opasatian  
1st Author's Affiliation The University of Tokyo (Tokyo Univ.)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (Tokyo Univ.)
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Speaker Author-1 
Date Time 2024-11-01 17:05:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # HWS2024-72, ICD2024-43 
Volume (vol) vol.124 
Number (no) no.229(HWS), no.230(ICD) 
Page pp.53-58 
#Pages 6 
Date of Issue 2024-10-25 (HWS, ICD) 

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