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Paper Abstract and Keywords
Presentation 2024-11-13 16:00
Cryogenic Transistor Current Modeling Based on Sparse Gaussian Process Regression
Tetsuro Iwasaki (KIT), Takashi Sato (KU), Michihiro Shintani (KIT) VLD2024-58 ICD2024-76 DC2024-80 RECONF2024-88
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we propose a method for modeling CMOS transistor characteristics under cryogenic con-
ditions using Sparse Gaussian process regression (SGPR). The temperature range of the standard transistor model
is from −55 ◦C to 125 ◦C, but applications operating at low temperatures are rapidly expanding. The proposed
method constructs a transistor current model to simulate CMOS circuits operating from room temperature to
cryogenic temperatures using SGPR, which is an approximate Gaussian process regression method. The proposed
method can simulate a wide range of bias conditions from the cutoff region to the saturation region by learning
low-current and high-current regions separately and connecting them smoothly with a smoothing function. In the
evaluation using nMOS and pMOS transistors fabricated on 65 nm and 22 nm processes, the model generated by
learning the current characteristics from 3 K to 300 K is incorporated into a commercial SPICE simulator, showing
that the simulation can be performed accurately.
Keyword (in Japanese) (See Japanese page) 
(in English) Compact modeling / Gaussian process regression / Cryo-CMOS / / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 247, VLD2024-58, pp. 177-182, Nov. 2024.
Paper # VLD2024-58 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-58 ICD2024-76 DC2024-80 RECONF2024-88

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2024-11-12 - 2024-11-14 
Place (in Japanese) (See Japanese page) 
Place (in English) COMPAL HALL 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2024 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2024-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Cryogenic Transistor Current Modeling Based on Sparse Gaussian Process Regression 
Sub Title (in English)  
Keyword(1) Compact modeling  
Keyword(2) Gaussian process regression  
Keyword(3) Cryo-CMOS  
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1st Author's Name Tetsuro Iwasaki  
1st Author's Affiliation Kyoto Institute of Technology (KIT)
2nd Author's Name Takashi Sato  
2nd Author's Affiliation Kyoto University (KU)
3rd Author's Name Michihiro Shintani  
3rd Author's Affiliation Kyoto Institute of Technology (KIT)
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Speaker Author-1 
Date Time 2024-11-13 16:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2024-58, ICD2024-76, DC2024-80, RECONF2024-88 
Volume (vol) vol.124 
Number (no) no.247(VLD), no.248(ICD), no.249(DC), no.250(RECONF) 
Page pp.177-182 
#Pages 6 
Date of Issue 2024-11-05 (VLD, ICD, DC, RECONF) 

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