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Paper Abstract and Keywords
Presentation 2025-01-16 09:00
Logic Gate Design Using Vertical Nanowire Transistor
Genta Nakamura (Kyushu Univ), Katsuhiro Tomioka (Hokkaido Univ), Koji Inoue (Kyushu Univ) VLD2024-76 RECONF2024-106
Abstract (in Japanese) (See Japanese page) 
(in English) As transistor miniaturization is reaching its limits, integrated circuit technology using novel devices and new computing technology are being investigated. In this study, we investigate the structure of logic gates using VGAA-TFETs, which consist of nanowire, and evaluate the area and path length. This paper describes the structure of a logic gate using VGAA-TFETs and the evaluation results.
Keyword (in Japanese) (See Japanese page) 
(in English) Logic Gate / Nanowire Transistor / 3D Circuit Structure / Low-Power Device / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 329, VLD2024-76, pp. 1-6, Jan. 2025.
Paper # VLD2024-76 
Date of Issue 2025-01-09 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-76 RECONF2024-106

Conference Information
Committee VLD RECONF  
Conference Date 2025-01-16 - 2025-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Yokohama Technology Campus Flagship Building 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2025-01-VLD-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Logic Gate Design Using Vertical Nanowire Transistor 
Sub Title (in English)  
Keyword(1) Logic Gate  
Keyword(2) Nanowire Transistor  
Keyword(3) 3D Circuit Structure  
Keyword(4) Low-Power Device  
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Keyword(6)  
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1st Author's Name Genta Nakamura  
1st Author's Affiliation Kyushu University (Kyushu Univ)
2nd Author's Name Katsuhiro Tomioka  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ)
3rd Author's Name Koji Inoue  
3rd Author's Affiliation Kyushu University (Kyushu Univ)
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Speaker Author-1 
Date Time 2025-01-16 09:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2024-76, RECONF2024-106 
Volume (vol) vol.124 
Number (no) no.329(VLD), no.330(RECONF) 
Page pp.1-6 
#Pages 6 
Date of Issue 2025-01-09 (VLD, RECONF) 

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