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Paper Abstract and Keywords
Presentation 2025-01-17 14:20
Emulation Environment for Reconfigurable Virtual Accelerator (ReVA) with QEMU
Kaoru Kayukawa, Shunya Kawai, Kazuki Yaguchi (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo, LCC.), Hironori Nakajo (TUAT) VLD2024-96 RECONF2024-126
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, hardware-based acceleration has become widespread in fields such as artificial intelligence (AI) and high-performance computing (HPC). However, as computational processes become more complex, hardware resource shortages have become a pressing issue. To address this problem, we have been conducting research on Reconfigurable Virtual Accelerator (ReVA). This paper clarifies the operation of tasks in ReVA and reports on the results of constructing an emulator for ReVA using the open-source QEMU emulator, incorporating communication via Compute Express Link (CXL).
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Hardware Acceleration / QEMU / Compute Express Link / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 330, RECONF2024-126, pp. 110-115, Jan. 2025.
Paper # RECONF2024-126 
Date of Issue 2025-01-09 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-96 RECONF2024-126

Conference Information
Committee VLD RECONF  
Conference Date 2025-01-16 - 2025-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Yokohama Technology Campus Flagship Building 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2025-01-VLD-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Emulation Environment for Reconfigurable Virtual Accelerator (ReVA) with QEMU 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Hardware Acceleration  
Keyword(3) QEMU  
Keyword(4) Compute Express Link  
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Keyword(6)  
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Keyword(8)  
1st Author's Name Kaoru Kayukawa  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Shunya Kawai  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Kazuki Yaguchi  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Yasunori Osana  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Takefumi Miyoshi  
5th Author's Affiliation Wasalabo, LCC. (Wasalabo, LCC.)
6th Author's Name Hironori Nakajo  
6th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2025-01-17 14:20:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2024-96, RECONF2024-126 
Volume (vol) vol.124 
Number (no) no.329(VLD), no.330(RECONF) 
Page pp.110-115 
#Pages 6 
Date of Issue 2025-01-09 (VLD, RECONF) 

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