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Paper Abstract and Keywords
Presentation 2025-03-06 15:55
Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda (The University of Tokyo) VLD2024-120 HWS2024-91 ICD2024-111
Abstract (in Japanese) (See Japanese page) 
(in English) This study explores accelerating single-source shortest path (SSSP) computations, including Dijkstra and A* algorithms, using high-level synthesis (HLS) and dynamic data structures. Current approaches focus on parallel node exploration with Multi Queue, nearest-node searches via memory partitioning, and parallel expansion of adjacent edges. However, these methods often require independent designs in traditional RTL implementations. The interdependence between node-parallel and edge-parallel searches introduces design complexity, limiting parallelism to a single aspect and underutilizing computational concurrency. Existing memory partitioning strategies also typically use fixed partitioning, which can degrade performance for varying graph types. To overcome these limitations, we propose an HLS-based method that optimizes queue processing with linked lists. During graph data writes, adjacent edges of the same node are automatically distributed across different memory partitions. This approach includes linked list and queue structures tailored for HLS, facilitating smooth migration of C++ code to FPGA hardware. By enabling pipeline parallelism for both node expansion and adjacent edge exploration, our design maximizes temporal and spatial concurrency. This results achieve near-linear speedup in cycles. In contrast, software parallelism exhibits a significant decline in performance beyond four parallel threads and requires graphs with more than 100 million nodes to achieve noticeable acceleration.
Keyword (in Japanese) (See Japanese page) 
(in English) High-Level Synthesis / Digital Design / single-source shortest path / Dijkstra / A-Star / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 400, VLD2024-120, pp. 96-101, March 2025.
Paper # VLD2024-120 
Date of Issue 2025-02-26 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-120 HWS2024-91 ICD2024-111

Conference Information
Committee HWS ICD VLD  
Conference Date 2025-03-05 - 2025-03-08 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2025-03-HWS-ICD-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation 
Sub Title (in English)  
Keyword(1) High-Level Synthesis  
Keyword(2) Digital Design  
Keyword(3) single-source shortest path  
Keyword(4) Dijkstra  
Keyword(5) A-Star  
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1st Author's Name Haopeng Meng  
1st Author's Affiliation The University of Tokyo (The University of Tokyo)
2nd Author's Name Kazutoshi Wakabayashi  
2nd Author's Affiliation The University of Tokyo (The University of Tokyo)
3rd Author's Name Makoto Ikeda  
3rd Author's Affiliation The University of Tokyo (The University of Tokyo)
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Speaker Author-1 
Date Time 2025-03-06 15:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2024-120, HWS2024-91, ICD2024-111 
Volume (vol) vol.124 
Number (no) no.400(VLD), no.401(HWS), no.402(ICD) 
Page pp.96-101 
#Pages 6 
Date of Issue 2025-02-26 (VLD, HWS, ICD) 

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