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Paper Abstract and Keywords
Presentation 2025-03-06 10:10
Design and evaluation of image processing architecture based on Network on Chip
Hayato Miyoshi, Rento Yoshihara, Ryuya Kadota, Kanto Kawakami, Masafumi Kondo (Okayama Science Univ.) VLD2024-111 HWS2024-82 ICD2024-102
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, GPUs have been widely used as image processing accelerators, and the number of cores on them continues to increase. We focus on Network on Chip, used as an interconnect for many cores and propose an image processing architecture based on packet routing. Although this architecture requires packets to be propagated in the spiral direction for the pixel values associated with the cores, the circuit structure of routers that control the direction of packet propagation has not been thoroughly considered. In this paper, we propose two circuit structures for the router: a method that simply controls the propagation direction using a multiplexer, and a method that propagates along the shortest path by connecting local ring buses. Furthermore, we design these router circuits and report the evaluation results.
Keyword (in Japanese) (See Japanese page) 
(in English) Network on Chip / image filtering / packet routing / ring bus / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 400, VLD2024-111, pp. 49-54, March 2025.
Paper # VLD2024-111 
Date of Issue 2025-02-26 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2024-111 HWS2024-82 ICD2024-102

Conference Information
Committee HWS ICD VLD  
Conference Date 2025-03-05 - 2025-03-08 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2025-03-HWS-ICD-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and evaluation of image processing architecture based on Network on Chip 
Sub Title (in English)  
Keyword(1) Network on Chip  
Keyword(2) image filtering  
Keyword(3) packet routing  
Keyword(4) ring bus  
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Keyword(6)  
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1st Author's Name Hayato Miyoshi  
1st Author's Affiliation Okayama Science University (Okayama Science Univ.)
2nd Author's Name Rento Yoshihara  
2nd Author's Affiliation Okayama Science University (Okayama Science Univ.)
3rd Author's Name Ryuya Kadota  
3rd Author's Affiliation Okayama Science University (Okayama Science Univ.)
4th Author's Name Kanto Kawakami  
4th Author's Affiliation Okayama Science University (Okayama Science Univ.)
5th Author's Name Masafumi Kondo  
5th Author's Affiliation Okayama Science University (Okayama Science Univ.)
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Speaker Author-1 
Date Time 2025-03-06 10:10:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2024-111, HWS2024-82, ICD2024-102 
Volume (vol) vol.124 
Number (no) no.400(VLD), no.401(HWS), no.402(ICD) 
Page pp.49-54 
#Pages 6 
Date of Issue 2025-02-26 (VLD, HWS, ICD) 

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