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Paper Abstract and Keywords
Presentation 2025-03-18 11:15
Design of Compute Unit of RISC-V ISA-based GPGPU
Keita Muto, Nobuyuki Yamasaki (Keio Univ.) CPSY2024-54 DC2024-125
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, parallel processing units, called GPGPU (General-Purpose Graphics Processing Unit), have been used for applications that process large amounts of data, such as machine learning and video processing. GPGPU is SIMT (Single Instruction Multiple Threads) architecture that performs parallel processing by using many threads. RISC-V is a free and open instruction set architecture (ISA) with a rich ecosystem, such as compiler tools. In this paper, we design a compute unit adding SIMD units in a GPGPU based on RISC-V ISA to improve processing efficiency.
Keyword (in Japanese) (See Japanese page) 
(in English) GPGPU / RISC-V / SIMD / SIMT / / / /  
Reference Info. IEICE Tech. Rep., vol. 124, no. 438, CPSY2024-54, pp. 55-60, March 2025.
Paper # CPSY2024-54 
Date of Issue 2025-03-10 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2024-54 DC2024-125

Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2025-03-17 - 2025-03-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Okierabu Floral Hotel 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2025 
Paper Information
Registration To CPSY 
Conference Code 2025-03-DC-CPSY-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Compute Unit of RISC-V ISA-based GPGPU 
Sub Title (in English)  
Keyword(1) GPGPU  
Keyword(2) RISC-V  
Keyword(3) SIMD  
Keyword(4) SIMT  
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1st Author's Name Keita Muto  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Nobuyuki Yamasaki  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2025-03-18 11:15:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2024-54, DC2024-125 
Volume (vol) vol.124 
Number (no) no.438(CPSY), no.439(DC) 
Page pp.55-60 
#Pages 6 
Date of Issue 2025-03-10 (CPSY, DC) 

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