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Paper Abstract and Keywords
Presentation 2025-09-18 15:55
[Invited Talk] Accelerating YOLOv3-tiny on an MPSoC FPGA -- A Report from an FPGA-AI Design Hackathon --
Musashi Otsuka, Atsuhiro Okamoto, Takayuki Suyama (OIT) RECONF2025-56
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we present a case study on accelerating the lightweight object detection model YOLOv3-tiny using AMD’s MPSoC FPGA platform, the KV260. This work was carried out during the “FPGA AI Design Hackathon” at the Hot SPring Annual Meeting 2025, with the goal of building a real-time inference pipeline.
We implemented AMD’s DPU (Deep-Learning Processing Unit) IP core on the FPGA and optimized the entire edge AI inference system, covering image input, preprocessing, inference, and rendering. In addition, we introduce the strategies employed for implementation and tuning within the limited timeframe, as well as the approaches to team-based development, and we discuss the challenges of deploying AI on FPGAs.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA AI Design Hackathon / YOLOv3-tiny / KV260 / / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 184, RECONF2025-56, pp. 22-27, Sept. 2025.
Paper # RECONF2025-56 
Date of Issue 2025-09-11 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2025-56

Conference Information
Committee RECONF  
Conference Date 2025-09-18 - 2025-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2025-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Accelerating YOLOv3-tiny on an MPSoC FPGA 
Sub Title (in English) A Report from an FPGA-AI Design Hackathon 
Keyword(1) FPGA AI Design Hackathon  
Keyword(2) YOLOv3-tiny  
Keyword(3) KV260  
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1st Author's Name Musashi Otsuka  
1st Author's Affiliation Osaka Institute of Technology (OIT)
2nd Author's Name Atsuhiro Okamoto  
2nd Author's Affiliation Osaka Institute of Technology (OIT)
3rd Author's Name Takayuki Suyama  
3rd Author's Affiliation Osaka Institute of Technology (OIT)
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Speaker Author-1 
Date Time 2025-09-18 15:55:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2025-56 
Volume (vol) vol.125 
Number (no) no.184 
Page pp.22-27 
#Pages 6 
Date of Issue 2025-09-11 (RECONF) 

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