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Paper Abstract and Keywords
Presentation 2025-09-19 14:45
Enhanced PAE Cell Architecture for eFPGA IP with Reduced Logic Cell Area
Tatsuya Sasaki, Souta Kohata, Ryo Iwasaki, Masahiro Iida (Kumamoto Univ.) RECONF2025-65
Abstract (in Japanese) (See Japanese page) 
(in English) We are currently proposing a new logic cell, the PAE Cell, as an alternative to LUTs for eFPGA IP. Since the PAE Cell has less configuration memory compared to LUTs, it contributes to suppressing the increase in chip area when integrating eFPGA into ASICs and SoCs, which is a key challenge for eFPGAs. However, the current PAE Cell is not necessarily optimal in its relationship between logical expression capability and area. Therefore, this study aims to further reduce chip area by proposing and evaluating an improved PAE Cell that optimizes configuration memory while maintaining logical expression capability. As a result, the improved PAE Cell proposed in this study achieved a logic cell count increase of only 23.4% compared to the conventional PAE Cell, while reducing configuration memory by 53.7% and the logic cell area by 56.9%. On
the other hand, we found that the increase in logic cell count can lead to an expansion of the routing area, which causes an increase in overall chip area. This highlights the need for an evaluation of logic cells that includes place-and-route.
Keyword (in Japanese) (See Japanese page) 
(in English) PA Cirkit / PAE Cell / Technology Mapping / eFPGA IP / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 184, RECONF2025-65, pp. 73-78, Sept. 2025.
Paper # RECONF2025-65 
Date of Issue 2025-09-11 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2025-09-18 - 2025-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2025-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Enhanced PAE Cell Architecture for eFPGA IP with Reduced Logic Cell Area 
Sub Title (in English)  
Keyword(1) PA Cirkit  
Keyword(2) PAE Cell  
Keyword(3) Technology Mapping  
Keyword(4) eFPGA IP  
Keyword(5)  
Keyword(6)  
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1st Author's Name Tatsuya Sasaki  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Souta Kohata  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Ryo Iwasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2025-09-19 14:45:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2025-65 
Volume (vol) vol.125 
Number (no) no.184 
Page pp.73-78 
#Pages 6 
Date of Issue 2025-09-11 (RECONF) 

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