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Paper Abstract and Keywords
Presentation 2025-11-07 16:55
Redesign of Low-Power Half-Flux-Quantum Logic Gates Considering Kinetic Inductance of π-Junctions
Masamitsu Tanaka, Soma Deguchi, Kenshin Inagaki, Kurato Toyama, Feng Li, Akira Fujimaki (Nagoya Univ.) SCE2025-10
Abstract (in Japanese) (See Japanese page) 
(in English) The half-flux-quantum (HFQ) logic features low-power operation utilizing a dc-SQUID containing a π-junction as a switching element. The SQUID exhibits two stable states corresponding to clockwise and counterclockwise circulating currents in the loop, resulting in a drastically lowered nominal critical current of the SQUID. We implement HFQ circuits using the 0-0-π SQUID structure, which is composed of two conventional Josephson junctions and a π-junction. The π-junction has a sufficiently large critical current and serves as just a phase shifter. In this study, we report that the asymmetric structure of the 0-0-π SQUID can cause difficulty in designing HFQ circuits. The imbalance due to the kinetic inductance of the π-junction results in variations in phase changes and switching behavior, depending on the direction of the circulating current within the SQUIDs. We have redesigned HFQ logic gates, carefully adjusting the branch inductance of 0-0-π SQUIDs, considering the kinetic inductance of π junctions. Our numerical simulation shows that the balanced 0-0-π SQUIDs improve the operating margins of HFQ logic gates.
Keyword (in Japanese) (See Japanese page) 
(in English) Half-flux-quantum circuit / π-phase shift Josephson Junction / SQUID / / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 231, SCE2025-10, pp. 18-22, Nov. 2025.
Paper # SCE2025-10 
Date of Issue 2025-10-31 (SCE) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2025-10

Conference Information
Committee SCE  
Conference Date 2025-11-07 - 2025-11-07 
Place (in Japanese) (See Japanese page) 
Place (in English) RIEC, Tohoku Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Superconducting Electronics 
Paper Information
Registration To SCE 
Conference Code 2025-11-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Redesign of Low-Power Half-Flux-Quantum Logic Gates Considering Kinetic Inductance of π-Junctions 
Sub Title (in English)  
Keyword(1) Half-flux-quantum circuit  
Keyword(2) π-phase shift Josephson Junction  
Keyword(3) SQUID  
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1st Author's Name Masamitsu Tanaka  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Soma Deguchi  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Kenshin Inagaki  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Kurato Toyama  
4th Author's Affiliation Nagoya University (Nagoya Univ.)
5th Author's Name Feng Li  
5th Author's Affiliation Nagoya University (Nagoya Univ.)
6th Author's Name Akira Fujimaki  
6th Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker Author-1 
Date Time 2025-11-07 16:55:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2025-10 
Volume (vol) vol.125 
Number (no) no.231 
Page pp.18-22 
#Pages 5 
Date of Issue 2025-10-31 (SCE) 

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