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Paper Abstract and Keywords
Presentation 2025-12-03 14:55
Computation-Reduction Techniques and Optimization Software for Variable-Parallel Reconfigurable Architectures
Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai (Hokkaido University.), Alexandre Schmid (EPFL), Kota Ando (Hokkaido University.) VLD2025-61 ICD2025-81 DC2025-94 RECONF2025-112
Abstract (in Japanese) (See Japanese page) 
(in English) We conduct hardware-software co-design for a variable-parallelism reconfigurable architecture under development. On the hardware side, we implement a zero-multiplication skipping mechanism that bypasses MAC operations when the corresponding weight is zero. On the software side, we adopt pruning aligned with this behavior (zero-skip-oriented pruning). Using VGG16 on CIFAR-10, our approach removes approximately 50% of the weights while limiting the accuracy loss to about 1.0 percentage point after fine-tuning. We further confirm that the computational workload decreases roughly in proportion to the pruning ratio. These results demonstrate the effectiveness of the proposed method for enabling efficient, low-power inference in edge AI systems.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable Processor / Neural Networks / CGRA / Network Pruning / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 263, RECONF2025-112, pp. 239-244, Dec. 2025.
Paper # RECONF2025-112 
Date of Issue 2025-11-24 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2025-61 ICD2025-81 DC2025-94 RECONF2025-112

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2025-12-01 - 2025-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Toyama International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2025 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2025-12-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Computation-Reduction Techniques and Optimization Software for Variable-Parallel Reconfigurable Architectures 
Sub Title (in English)  
Keyword(1) Reconfigurable Processor  
Keyword(2) Neural Networks  
Keyword(3) CGRA  
Keyword(4) Network Pruning  
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1st Author's Name Yu Inoue  
1st Author's Affiliation Hokkaido University (Hokkaido University.)
2nd Author's Name Atsushi Hori  
2nd Author's Affiliation Hokkaido University (Hokkaido University.)
3rd Author's Name Takao Marukame  
3rd Author's Affiliation Hokkaido University (Hokkaido University.)
4th Author's Name Tetsuya Asai  
4th Author's Affiliation Hokkaido University (Hokkaido University.)
5th Author's Name Alexandre Schmid  
5th Author's Affiliation Swiss Federal Institute of Technology Lausanne (EPFL)
6th Author's Name Kota Ando  
6th Author's Affiliation Hokkaido University (Hokkaido University.)
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Speaker Author-1 
Date Time 2025-12-03 14:55:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # VLD2025-61, ICD2025-81, DC2025-94, RECONF2025-112 
Volume (vol) vol.125 
Number (no) no.260(VLD), no.261(ICD), no.262(DC), no.263(RECONF) 
Page pp.239-244 
#Pages 6 
Date of Issue 2025-11-24 (VLD, ICD, DC, RECONF) 

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