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Paper Abstract and Keywords
Presentation 2026-01-29 13:10
An FeFET-based Analog Silicon Neuron Circuit Model
Takahiro Saeki, Myoungsu Chae, Takashi Kohno (UTokyo) NLP2025-104 MBE2025-44 NC2025-66
Abstract (in Japanese) (See Japanese page) 
(in English) To reproduce complex neuronal dynamics on analog silicon neuron (ASiN)
circuits, a large number of transistor bias voltages has to be
appropriately configured.
In this study, we constructed an ASiN circuit model implemented using
ferroelectric field-effect transistors (FeFETs), which enables
nonvolatile storage of gate offset voltages. We demonstrate the
feasibility of the ASiN circuit which can be configured to exhibit
various neuronal firing classes.
Keyword (in Japanese) (See Japanese page) 
(in English) Analog Neuron Circuit / Ultra-Low Power Circuit / FeFET / Nonlinear Dynamics / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 346, NC2025-66, pp. 86-91, Jan. 2026.
Paper # NC2025-66 
Date of Issue 2026-01-21 (NLP, MBE, NC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NLP2025-104 MBE2025-44 NC2025-66

Conference Information
Committee NC MBE NLP IEE-MBE  
Conference Date 2026-01-28 - 2026-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu Institute of Technology, Wakamatsu Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) NC, NLP, ME, etc. 
Paper Information
Registration To NC 
Conference Code 2026-01-NC-MBE-NLP-MBE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FeFET-based Analog Silicon Neuron Circuit Model 
Sub Title (in English)  
Keyword(1) Analog Neuron Circuit  
Keyword(2) Ultra-Low Power Circuit  
Keyword(3) FeFET  
Keyword(4) Nonlinear Dynamics  
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Keyword(6)  
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1st Author's Name Takahiro Saeki  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Myoungsu Chae  
2nd Author's Affiliation The University of Tokyo (UTokyo)
3rd Author's Name Takashi Kohno  
3rd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2026-01-29 13:10:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NLP2025-104, MBE2025-44, NC2025-66 
Volume (vol) vol.125 
Number (no) no.344(NLP), no.345(MBE), no.346(NC) 
Page pp.86-91 
#Pages 6 
Date of Issue 2026-01-21 (NLP, MBE, NC) 

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