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Paper Abstract and Keywords
Presentation 2026-01-29 10:45
Digital Circuit Design of a High-Throughput Spike Communication Module Toward Large-Scale Spiking Neural Network Hardware
Yuki Majima, Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato (Tohoku Univ.) NLP2025-101 MBE2025-41 NC2025-63
Abstract (in Japanese) (See Japanese page) 
(in English) One promising approach to increasing the network scale of spiking neural network (SNN) hardware is the interconnection of multiple SNN chips. However, at high operating speeds, the communication traffic between SNN chips scales with the number of spike events, leading to a performance bottleneck. In this research, we designed a high-speed digital-circuit-based AER (Address Event Representation) module that enables the transmission and reception of spike events within a specified time window. The module consists of a transmitter and a receiver. We optimized the communication protocol to efficiently transmit spike events from 256 neurons over a 16-bit data bus. The transmitter communicates using the minimum number of clock cycles proportional to the number of spike events, while the receiver converts AER packets into spikes and transmits them to an analog SNN circuit. The proposed circuit was implemented at the RTL level using SystemVerilog. Logic simulations verified that AER packet transmission and reception are completed even under the worst-case condition in which all neurons generate spikes simultaneously. These results demonstrate the feasibility of scaling network size in analog SNN circuits through high-speed multi-chip implementation.
Keyword (in Japanese) (See Japanese page) 
(in English) Spiking neural network / digital circuit / address event representation / neuromorphic hardware / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 346, NC2025-63, pp. 74-74, Jan. 2026.
Paper # NC2025-63 
Date of Issue 2026-01-21 (NLP, MBE, NC) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NLP2025-101 MBE2025-41 NC2025-63

Conference Information
Committee NC MBE NLP IEE-MBE  
Conference Date 2026-01-28 - 2026-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu Institute of Technology, Wakamatsu Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) NC, NLP, ME, etc. 
Paper Information
Registration To NC 
Conference Code 2026-01-NC-MBE-NLP-MBE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Digital Circuit Design of a High-Throughput Spike Communication Module Toward Large-Scale Spiking Neural Network Hardware 
Sub Title (in English)  
Keyword(1) Spiking neural network  
Keyword(2) digital circuit  
Keyword(3) address event representation  
Keyword(4) neuromorphic hardware  
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1st Author's Name Yuki Majima  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Satoshi Moriya  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Hideaki Yamamoto  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Shigeo Sato  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2026-01-29 10:45:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NLP2025-101, MBE2025-41, NC2025-63 
Volume (vol) vol.125 
Number (no) no.344(NLP), no.345(MBE), no.346(NC) 
Page p.74 
#Pages 1 
Date of Issue 2026-01-21 (NLP, MBE, NC) 

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