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Paper Abstract and Keywords
Presentation 2026-03-06 15:45
Output Phase Control of a Subsampling PLL Using Phase-Controlled Clock and Reference Signals in a S/H Circuit
Osamu Wada, Hideyuki Nakamizo, Nobuhiko Ando (Mitsubishi Electric) MW2025-221
Abstract (in Japanese) (See Japanese page) 
(in English) In APAA systems, precise control of the phase difference between transmitted and received signals is required. In this paper, an output phase control of a subsampling PLL using phase-controlled clock and reference signals in a S/H circuit is proposed. The method is implemented by controlling the phases of the clock signal and the reference signal applied to the S/H circuit. Since the phase of the clock signal in the sub-sampling PLL is multiplied by an integer n (where n is a positive integer), large phase adjustments can be realized. Conversely, the phase of the reference signal is directly observed without multiplication, enabling fine phase steps. Measurement results show that desired phase control performance is obtained. The measured maximum phase error was 0.742°, and the maximum RMS phase error was 0.468°.
Keyword (in Japanese) (See Japanese page) 
(in English) Sub-sampling PLL / S/H circuit / Sub-sampling / Undersampling / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 394, MW2025-221, pp. 135-138, March 2026.
Paper # MW2025-221 
Date of Issue 2026-02-26 (MW) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF MW2025-221

Conference Information
Committee MW  
Conference Date 2026-03-05 - 2026-03-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Setoda city hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Microwave, etc. 
Paper Information
Registration To MW 
Conference Code 2026-03-MW 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Output Phase Control of a Subsampling PLL Using Phase-Controlled Clock and Reference Signals in a S/H Circuit 
Sub Title (in English)  
Keyword(1) Sub-sampling PLL  
Keyword(2) S/H circuit  
Keyword(3) Sub-sampling  
Keyword(4) Undersampling  
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1st Author's Name Osamu Wada  
1st Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
2nd Author's Name Hideyuki Nakamizo  
2nd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
3rd Author's Name Nobuhiko Ando  
3rd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
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Speaker Author-1 
Date Time 2026-03-06 15:45:00 
Presentation Time 25 minutes 
Registration for MW 
Paper # MW2025-221 
Volume (vol) vol.125 
Number (no) no.394 
Page pp.135-138 
#Pages 4 
Date of Issue 2026-02-26 (MW) 

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