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Paper Abstract and Keywords
Presentation 2026-03-07 12:15
Implementation and Evaluation of a Lightweight Countermeasure against Fault Attacks based on Redundant Instruction Fetch
Shoei Nashimoto, Naoya Okada, Yuichiro Murachi (Mitsubishi Electric) VLD2025-120 HWS2025-116 ICD2025-131
Abstract (in Japanese) (See Japanese page) 
(in English) Fault attacks pose a serious threat to embedded devices, and lightweight countermeasures are required in cost-constrained environments. This paper focuses on instruction fetch skipping, which is one of the most fundamental principles used to explain fault attacks, and proposes a lightweight countermeasure that introduces redundancy only in the fetch stage of the processor. The proposed method is implemented on a custom-designed RISC-V processor, and both performance evaluation and attack resistance evaluation are conducted. The results show that (1) the overheads in terms of FPGA resource usage and execution time are limited to 15.0% and 16.1%, respectively, and (2) the attack success rate is reduced to at most 0.13%, while at least 11.4% of attacks can be detected.
Keyword (in Japanese) (See Japanese page) 
(in English) Fault injection attack / Countermeasure / Processor / / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 383, HWS2025-116, pp. 248-253, March 2026.
Paper # HWS2025-116 
Date of Issue 2026-02-25 (VLD, HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2025-120 HWS2025-116 ICD2025-131

Conference Information
Committee ICD HWS VLD  
Conference Date 2026-03-04 - 2026-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To HWS 
Conference Code 2026-03-ICD-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of a Lightweight Countermeasure against Fault Attacks based on Redundant Instruction Fetch 
Sub Title (in English)  
Keyword(1) Fault injection attack  
Keyword(2) Countermeasure  
Keyword(3) Processor  
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1st Author's Name Shoei Nashimoto  
1st Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
2nd Author's Name Naoya Okada  
2nd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
3rd Author's Name Yuichiro Murachi  
3rd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
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Speaker Author-1 
Date Time 2026-03-07 12:15:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # VLD2025-120, HWS2025-116, ICD2025-131 
Volume (vol) vol.125 
Number (no) no.382(VLD), no.383(HWS), no.384(ICD) 
Page pp.248-253 
#Pages 6 
Date of Issue 2026-02-25 (VLD, HWS, ICD) 

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