Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2026-03-15 12:15
Defense Mechanism for TEE Interrupts to Minimize Software Dependency
Akihiro Saiki, Hidetoshi Uranami (Waseda Univ.), Kazuhide Uchiyama (ROIS/SOKENDAI/NII), Masahiro Goshima (ROIS/NII/SOKENDAI), Keiji Kimura (Waseda Univ.) CPSY2025-52 DC2025-124
Abstract (in Japanese) (See Japanese page) 
(in English) Conventional Trusted Execution Environments (TEEs) typically rely on defense mechanisms implemented in privileged software—often referred to as a TEE Security Module (TSM)—or dedicated co-processors, such as secure processors. This reliance leads to a large software Trusted Computing Base (TCB) and an expanded attack surface, thereby increasing the risk of undermining the intended security guarantees. To address these issues, the Universal TEE Architecture (UTA) proposed by the TriniTEE project advocates for the exclusion of privileged software and secure processors. By leveraging TEE hardware and cryptographic primitives, UTA facilitates the secure delegation of traditional TCB functions to untrusted software, such as hypervisors and operating systems. However, side-channel attacks exploiting CPU caches, branch prediction, or power consumption remain a significant threat. In particular, attacks leveraging single-stepping are particularly severe, as they enable high temporal resolution and fine-grained monitoring of instruction execution. While mitigating single-stepping is essential for side-channel defense, preventing it solely through TEE hardware is challenging because single-stepping typically relies on manipulating interrupts. This paper proposes a defense mechanism against interrupt abuse in TEEs within the UTA framework. Our method operates without privileged software or secure processors and maintains minimal software dependencies to ensure robust security.
Keyword (in Japanese) (See Japanese page) 
(in English) TEEs / Side-Channel Attack / Single-Stepping / / / / /  
Reference Info. IEICE Tech. Rep., vol. 125, no. 401, CPSY2025-52, pp. 1-6, March 2026.
Paper # CPSY2025-52 
Date of Issue 2026-03-08 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2025-52 DC2025-124

Conference Information
Committee DC CPSY IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2026-03-15 - 2026-03-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Sun-Olive Olive Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2026 
Paper Information
Registration To CPSY 
Conference Code 2026-03-DC-CPSY-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Defense Mechanism for TEE Interrupts to Minimize Software Dependency 
Sub Title (in English)  
Keyword(1) TEEs  
Keyword(2) Side-Channel Attack  
Keyword(3) Single-Stepping  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Akihiro Saiki  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Hidetoshi Uranami  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Kazuhide Uchiyama  
3rd Author's Affiliation ROIS/The Graduate University for Advanced Studies/National Institute of Informatics (ROIS/SOKENDAI/NII)
4th Author's Name Masahiro Goshima  
4th Author's Affiliation ROIS/National Institute of Informatics/The Graduate University for Advanced Studies (ROIS/NII/SOKENDAI)
5th Author's Name Keiji Kimura  
5th Author's Affiliation Waseda University (Waseda Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2026-03-15 12:15:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2025-52, DC2025-124 
Volume (vol) vol.125 
Number (no) no.401(CPSY), no.402(DC) 
Page pp.1-6 
#Pages 6 
Date of Issue 2026-03-08 (CPSY, DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan