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Paper Abstract and Keywords
Presentation 2026-05-14 09:30
CPU-Idle-Aware Task-Specific Scheduling for Reducing Packet-Processing Latency
Ko Natori (NTT/Keio Univ.), Ikuo Otani, Kei Fujimoto (NTT), Kenji Kono (Keio Univ.) NS2026-18
Abstract (in Japanese) (See Japanese page) 
(in English) General-purpose OSes typically adopt workload-agnostic task-management policies to provide fairness and broad applicability across diverse workloads. However, such uniform policies can sometimes introduce inefficiencies. In this paper, we demonstrate one such case in packet processing: when kernel-side packet reception and an application thread waiting for incoming packets are executed on different CPU cores, application latency increases because both cores may incur the cost of waking up from deep CPU idle states. To mitigate this problem, we propose a method that uses the OS tracing mechanisms and the sched_ext scheduler extension framework to introduce CPU-idle-aware task-specific scheduling logic. Specifically, the method steers packet reception and the application thread onto the same core. Our implementation and evaluation demonstrate that the proposed method can reduce application latency.
Keyword (in Japanese) (See Japanese page) 
(in English) Low Latency / Energy Efficiency / Operating System / / / / /  
Reference Info. IEICE Tech. Rep., vol. 126, no. 21, NS2026-18, pp. 1-9, May 2026.
Paper # NS2026-18 
Date of Issue 2026-05-07 (NS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NS2026-18

Conference Information
Committee NS  
Conference Date 2026-05-14 - 2026-05-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Hakata Kindai Building + Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) High level protocol, Networking technologies (IP and high-layer routing/filtering, Multicast, Quality/Routing control), IP network application technologies (P2P, P4P, Overlay, SIP, NGN), Network system related technologies (System configuration, Interface, Architecture, Hardware/Software/Middleware), Security, Blockchain etc. 
Paper Information
Registration To NS 
Conference Code 2026-05-NS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) CPU-Idle-Aware Task-Specific Scheduling for Reducing Packet-Processing Latency 
Sub Title (in English)  
Keyword(1) Low Latency  
Keyword(2) Energy Efficiency  
Keyword(3) Operating System  
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1st Author's Name Ko Natori  
1st Author's Affiliation Network Innovation Center, NTT, Inc./Keio University (NTT/Keio Univ.)
2nd Author's Name Ikuo Otani  
2nd Author's Affiliation Network Innovation Center, NTT, Inc. (NTT)
3rd Author's Name Kei Fujimoto  
3rd Author's Affiliation Network Innovation Center, NTT, Inc. (NTT)
4th Author's Name Kenji Kono  
4th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2026-05-14 09:30:00 
Presentation Time 25 minutes 
Registration for NS 
Paper # NS2026-18 
Volume (vol) vol.126 
Number (no) no.21 
Page pp.1-9 
#Pages 9 
Date of Issue 2026-05-07 (NS) 

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