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Paper Abstract and Keywords
Presentation 2026-06-01 16:30
Reduction of Processing for FPGA-Parallelization of a Piano Simulator
Masatsugu Okazaki, Eiji Tominaga (YAMAHA) CPSY2026-3 DC2026-3 RECONF2026-3
Abstract (in Japanese) (See Japanese page) 
(in English) We analyzed the computational, memory, and parallelization characteristics of a three-dimensional finite‑element–based piano simulation for real-time hardware implementation. Even after modal synthesis and reduction to the audible frequency range, the model retains tens of thousands of degrees of freedom, requiring heavy computation to update string–hammer–body interactions in real time, far exceeding the capabilities of CPUs and GPUs.
The analysis identified large matrix–vector multiplications at string–body junctions and limited parallelism in the string, hammer, damper, and longitudinal vibration models as the main bottlenecks.
By reducing direction-dependent string–body coupling points and body vibration modes while preserving sound quality, we significantly reduced computational and memory requirements, enabling a processing scale initially estimated to require dozens of FPGAs to be implemented using only a few devices, and demonstrating a practical path to real-time physical‑model piano sound synthesis.
Keyword (in Japanese) (See Japanese page) 
(in English) Piano Physical Model / FEM / Modal synthesis / Time-domain Simulation / Real-Time Processing / Parallel Processing / FPGA Implementation /  
Reference Info. IEICE Tech. Rep., vol. 126, no. 51, RECONF2026-3, pp. 11-16, June 2026.
Paper # RECONF2026-3 
Date of Issue 2026-05-25 (CPSY, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2026-3 DC2026-3 RECONF2026-3

Conference Information
Committee CPSY DC RECONF IPSJ-ARC  
Conference Date 2026-06-01 - 2026-06-03 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To RECONF 
Conference Code 2026-06-CPSY-DC-RECONF-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reduction of Processing for FPGA-Parallelization of a Piano Simulator 
Sub Title (in English)  
Keyword(1) Piano Physical Model  
Keyword(2) FEM  
Keyword(3) Modal synthesis  
Keyword(4) Time-domain Simulation  
Keyword(5) Real-Time Processing  
Keyword(6) Parallel Processing  
Keyword(7) FPGA Implementation  
Keyword(8)  
1st Author's Name Masatsugu Okazaki  
1st Author's Affiliation YAMAHA Corporation (YAMAHA)
2nd Author's Name Eiji Tominaga  
2nd Author's Affiliation YAMAHA Corporation (YAMAHA)
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Speaker Author-1 
Date Time 2026-06-01 16:30:00 
Presentation Time 20 minutes 
Registration for RECONF 
Paper # CPSY2026-3, DC2026-3, RECONF2026-3 
Volume (vol) vol.126 
Number (no) no.49(CPSY), no.50(DC), no.51(RECONF) 
Page pp.11-16 
#Pages 6 
Date of Issue 2026-05-25 (CPSY, DC, RECONF) 

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