This paper describes a hybrid wave-pipelined adder using a gain based delay model in order to balance the delays in a combinational logic circuit. Hybrid wave-pipeline technique combines traditional pipeline techniques with wave-pipeline concepts. It allows multiple data waves to exist in any stage similar to wave-pipelining. The delay difference in a hybrid wave-pipelined architecture can be minimized by inserting delay elements. It is proposed in this paper to use these delay elements for rough tuning and gate sizing, based on the effort delay model meant for fine tuning. The experimental results show that the hybrid wave-pipelined adder using our proposed delay balancing tools operates at frequencies higher than conventional pipelined and wave-pipelined adders.
(英)
This paper describes a hybrid wave-pipelined adder using a gain based delay model in order to balance the delays in a combinational logic circuit. Hybrid wave-pipeline technique combines traditional pipeline techniques with wave-pipeline concepts. It allows multiple data waves to exist in any stage similar to wave-pipelining. The delay difference in a hybrid wave-pipelined architecture can be minimized by inserting delay elements. It is proposed in this paper to use these delay elements for rough tuning and gate sizing, based on the effort delay model meant for fine tuning. The experimental results show that the hybrid wave-pipelined adder using our proposed delay balancing tools operates at frequencies higher than conventional pipelined and wave-pipelined adders.