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Technical Committee on Dependable Computing (DC)  (Searched in: 2011)

Search Results: Keywords 'from:2011-04-12 to:2011-04-12'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY 2011-04-12
13:00		 Tokyo   An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults
Satoshi Fukumoto, Kenta Imai, Hideo Kohinata, Masayuki Arai (Tokyo Metropolitan Univ.) CPSY2011-1 DC2011-1		 This paper discusses the extension of highly reliable technique for sequential circuits using duplicate register which h... [more] CPSY2011-1 DC2011-1
pp.1-4
DC, CPSY 2011-04-12
13:25		 Tokyo   A Note on Data Compression of Double-Precision Floating-Point Numbers for Massively Parallel Numerical Simulations
Mamoru Ohara, Takashi Yamaguchi (TIRI) CPSY2011-2 DC2011-2		 In numerical simulations using massively parallel computers like GPGPU (General-Purpose computing on Graphics Processing... [more] CPSY2011-2 DC2011-2
pp.5-10
DC, CPSY 2011-04-12
13:50		 Tokyo   A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
Chammika Mannakkara, Daihan Wang, Vijay Holimath, Tomohiro Yoneda (NII) CPSY2011-3 DC2011-3		 This report presents our first trial to apply a Network-on-Chip (NoC)
architecture to a gasoline engine control, one of... [more]		 CPSY2011-3 DC2011-3
pp.11-16
DC, CPSY 2011-04-12
14:30		 Tokyo   [Invited Talk] Tamper LSI Design Methodology Resistant to Malicious Attack
Takeshi Fujino, Mitsuru Shiozaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.) CPSY2011-4 DC2011-4		 Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant t... [more] CPSY2011-4 DC2011-4
pp.17-22
DC, CPSY 2011-04-12
15:45		 Tokyo   Transient-Fault-Tolerant Out-of-Order Superscalar Processor
Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima, Shuichi Sakai (The Univ. of Tokyo) CPSY2011-5 DC2011-5		 Recently, LSI is shrinking and random-variability problem is increasing. For further growth of semiconductor industry, c... [more] CPSY2011-5 DC2011-5
pp.23-28
DC, CPSY 2011-04-12
16:10		 Tokyo   Note on Defect Level Evaluation of Cascaded TMR for Pipeline Processors
Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.) CPSY2011-6 DC2011-6		  [more] CPSY2011-6 DC2011-6
pp.29-34
DC, CPSY 2011-04-12
16:35		 Tokyo   Highly Flexible Task Tracer IP for the Real-Time OS on FPGA/SoC Environments
Yuji Takeda, Mamoru Ohara, Tadashi Okabe, Ken Sato (Tokyo Metro. Indust. Tech. Res. Inst.) CPSY2011-7 DC2011-7		 Recently, the use of RTOS is advanced in a multi-core processor on FPGA/SoC, and to watch the task transitions is import... [more] CPSY2011-7 DC2011-7
pp.35-40
 Results 1 - 7 of 7  /   
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