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| Chair |
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Masao Nakaya |
| Vice Chair |
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Akira Matsuzawa |
| Secretary |
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Koji Kai, Yoshiharu Aimoto |
| Assistant |
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Makoto Nagata, Minoru Fujishima |
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|
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| Chair |
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Hiroshi Nakamura |
| Secretary |
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Makoto Satoh, Kenji Kise |
| Assistant |
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Atsushi Mori, Koji Inoue |
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| Conference Date |
Thu, Jun 8, 2006 10:00 - 17:00
Fri, Jun 9, 2006 09:30 - 17:45 |
| Topics |
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| Conference Place |
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Thu, Jun 8 AM
10:00 - 13:00 |
| (1) |
10:00-10:30 |
A Case for Hot-Path-based Branch Prediction |
Kosuke Tsuiji, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
| (2) |
10:30-11:00 |
A Low-Power, Reliable Datapath by Reusing Execution Results |
Yosuke Hashiguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ) |
| (3) |
11:00-11:30 |
Reducing Energy Consumption of the Dynamic Scheduling Logic by Instruction Grouping |
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
| (4) |
11:30-12:00 |
Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection |
Jun Yao, Hajime Shimada (Kyoto Univ.), Yasuhiko Nakashima (NAIST), Shin-ichiro Mori (Fukui Univ.), Shinji Tomita (Kyoto Univ.) |
| |
12:00-13:00 |
Lunch Break ( 60 min. ) |
Thu, Jun 8 PM
13:00 - 13:50 |
| (5) |
13:00-13:50 |
[Special Invited Talk]
The need of a collaboration between the computer architecture and the integrated circuit technology |
Hisashige Ando (Fujitsu Ltd.) |
| |
13:50-14:00 |
Break ( 10 min. ) |
Thu, Jun 8 PM
14:00 - 16:00 |
| (6) |
14:00-14:30 |
50% power reduction in H.264/AVC HDTV decoder LSI by dynamic voltage/frequency scaling with elastic pipeline architecture |
Kentaro Kawakami (Kobe Univ.), Jun Takemura (Renesas), Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
| (7) |
14:30-15:00 |
Physical Register Access Analysis for Temperature-Aware Microarchitecture |
Toshinori Sato (Kyushu Univ.), Yuji Kunitake, Akihiro Chiyonobu (Kyushu Inst. Tech.) |
| (8) |
15:00-15:30 |
Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation |
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka (Kyushu Inst. Tech.), Toshinori Sato (Kyushu Univ.) |
| (9) |
15:30-16:00 |
Design for Testability of Software-Based Self-Test for Processors |
Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
| |
16:00-16:10 |
Break ( 10 min. ) |
Thu, Jun 8 PM
16:10 - 17:00 |
| (10) |
16:10-17:00 |
[Special Invited Talk]
Discussing the national next-generation supercomputer from the viewpoint of LSI technology and computer architecture |
Kazuaki Murakami (Kyushu Univ.) |
Fri, Jun 9 AM
09:30 - 11:00 |
| (11) |
09:30-10:00 |
Voltage/Current-Control-Based Low-Power Design of a Multiple-Valued Reconfigurable VLSI |
Nobuaki Okada, Haque Mohammad Munirul, Michitaka Kameyama (Tohoku Univ.) |
| (12) |
10:00-10:30 |
Dynamically Reconfigurable Architecture for Road Extraction |
Sunge Lee, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
| (13) |
10:30-11:00 |
A Reconfigurable Functional Unit for Adaptable Custom Instructions |
Hamid Noori (Kyushu Univ.), Farhad Mehdipour (Amirkabir Univ. of Tech.), Kazuaki Murakami, Koji Inoue (Kyushu Univ.), Morteza Saheb Zamani (Amirkabir Univ. of Tech.) |
| |
11:00-11:10 |
Break ( 10 min. ) |
Fri, Jun 9 AM
11:10 - 12:00 |
| (14) |
11:10-12:00 |
[Special Invited Talk]
Architecture and Circuit, How to Collaborate ? |
Naoki Nishi (NEC) |
| |
12:00-13:00 |
Lunch Break ( 60 min. ) |
Fri, Jun 9 PM
13:00 - 15:30 |
| (15) |
13:00-13:30 |
A Superscalar employing Instruction Decomposition for ARM Architecture |
Yasuhiko Nakashima (NAIST) |
| (16) |
13:30-14:00 |
A VLIW Single-Chip Multi-Processor for Multimedia processing |
Masahiko Toichi, Atsuhiro Suga, Fumihiko Hayakawa, Shinichiro Tago, Satoshi Imai, Atsushi Tanaka (Fujitsu Lab) |
| (17) |
14:00-14:30 |
Design of a High Performance Vision Processor with Shared Memory Multi-SIMD Architecture |
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa (The University of Tokyo) |
| (18) |
14:30-15:00 |
Optimal Memory Allocation for Image Processors |
Masanori Hariyama (Tohoku Univ.), Yasuhiro Kobayashi (Oyama National College of Tech.), Michitaka Kameyama (Tohoku Univ.) |
| (19) |
15:00-15:30 |
A Virtual-Channel Free Mapping for On-Chip Torus Networks |
Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Fri, Jun 9 PM
15:45 - 17:45 |
| (20) |
15:45-17:45 |
[Panel Discussion]
How do we create combining architecture and integrated circuits? |
Kunio Uchiyama (Hitachi, Ltd.,) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 10 minutes for discussion. |
| Special Invited Talk | Each speech will have 40 minutes for presentation and 10 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Koji Kai(Matsuhita Electric Industrial Co., Ltd.)
E- : i-icd ml  pa   c |
| IPSJ-ARC |
Special Interest Group on Computer Architecture (IPSJ-ARC) [Latest Schedule]
|
| Contact Address |
Koji Inoue(Kyushu University)
E-:i  ik shu-u |
Last modified: 2006-05-19 00:00:13
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