|
|
| Chair |
|
Kentaro Sano (RIKEN) |
| Vice Chair |
|
Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.) |
| Secretary |
|
Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.) |
| Assistant |
|
Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.) |
|
| Conference Date |
Fri, Sep 10, 2021 09:30 - 16:35 |
| Topics |
Reconfigurable system, etc. |
| Conference Place |
|
Contact
Person |
Yukitaka Takemura, Intel |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF. |
Fri, Sep 10 AM AI Application
09:30 - 10:45 |
| (1) |
09:30-09:55 |
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA  RECONF2021-17 |
Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech) |
| (2) |
09:55-10:20 |
An FPGA Implementation of neural networks with multi-core structured using high level synthesis RECONF2021-18 |
Akira Jinguji, Hiroki Nakahara (Tokyo Tech) |
| (3) |
10:20-10:45 |
Convolutional neural network implementations using Vitis AI RECONF2021-19 |
Akihiko Ushiroyama, Nobuya Watanabe, Akira Nagoya, Minoru Watanabe (Okayama Univ.) |
| |
10:45-11:00 |
Break ( 15 min. ) |
| |
11:00-12:45 |
Lunch break (RECONF Research Committee meeting will be held.) ( 105 min. ) |
Fri, Sep 10 PM
12:45 - 13:00 |
| (4) |
12:45-13:00 |
|
Fri, Sep 10 PM Invited Talk
13:00 - 13:50 |
| (5) |
13:00-13:50 |
[Invited Talk]
Development of a very high-speed, low power computer system for Deep Learning at Preferred Networks |
Kei Hiraki (PFN) |
| |
13:50-14:10 |
Break ( 20 min. ) |
Fri, Sep 10 PM FPGA Application 1
14:10 - 15:25 |
| (6) |
14:10-14:35 |
RECONF2021-20 |
|
| (7) |
14:35-15:00 |
RECONF2021-21 |
|
| (8) |
15:00-15:25 |
Parallel Calculation of Local Scores in Bayesian Network Structure Learning using FPGA RECONF2021-22 |
Ryota Miyagi (Kyoto Univ.), Hideki Takase (U. Tokyo/JST) |
| |
15:25-15:45 |
Break ( 20 min. ) |
Fri, Sep 10 PM FPGA Application 2
15:45 - 16:35 |
| (9) |
15:45-16:10 |
RECONF2021-23 |
|
| (10) |
16:10-16:35 |
Multi-FPGA Based Hardware Acceleration for Genetic Data Analysis RECONF2021-24 |
Imdad Ullah (Keio Univ.), Akram Ben Ahmed (AIST), Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Last modified: 2021-09-10 09:40:11
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