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Paper Abstract and Keywords
Presentation 2021-09-10 09:30
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA
Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech) RECONF2021-17
Abstract (in Japanese) (See Japanese page) 
(in English) Convolutional neural networks (CNNs) are widely used for image processing tasks in both embedded systems and data centers.
In data centers, high accuracy and low latency are desired for various tasks such as image processing of streaming videos.
We propose an FPGA-based low-latency CNN inference for randomly wired convolutional neural networks (RWCNNs), whose layer structures are based on random graph models.
Because RWCNNs have several convolution layers that have no direct dependencies between them, our architecture can process them efficiently using a pipeline method.
At each layer, we need to use the calculation results of multiple layers as the input.
We use an FPGA with HBM2 to enable parallel access to the input data with multiple HBM2 channels.
We schedule the order of execution of the layers to improve the pipeline efficiency.
We build a conflict graph using the scheduling results.
Then, we allocate the calculation results of each layer to the HBM2 channels by coloring the graph.
We implemented the proposed architecture on the Alveo U50 FPGA.
We obtained 12.6 and 4.93 times better efficiency than CPU and GPU, respectively.
Keyword (in Japanese) (See Japanese page) 
(in English) Deep Learning / CNN / FPGA / RWCNN / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 175, RECONF2021-17, pp. 1-6, Sept. 2021.
Paper # RECONF2021-17 
Date of Issue 2021-09-03 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2021-17

Conference Information
Committee RECONF  
Conference Date 2021-09-10 - 2021-09-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable system, etc. 
Paper Information
Registration To RECONF 
Conference Code 2021-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA 
Sub Title (in English)  
Keyword(1) Deep Learning  
Keyword(2) CNN  
Keyword(3) FPGA  
Keyword(4) RWCNN  
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1st Author's Name Ryosuke Kuramochi  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Hiroki Nakahara  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2021-09-10 09:30:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2021-17 
Volume (vol) vol.121 
Number (no) no.175 
Page pp.1-6 
#Pages 6 
Date of Issue 2021-09-03 (RECONF) 

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