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| Chair |
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MIchitaka Kameyama |
| Vice Chair |
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Masao Nakaya |
| Secretary |
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Kunio Uchiyama, Shinji Miyano |
| Assistant |
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Masanori Hariyama, Koji Kai |
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| Conference Date |
Thu, Dec 16, 2004 10:00 - 17:15
Fri, Dec 17, 2004 10:00 - 15:00 |
| Topics |
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| Conference Place |
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Thu, Dec 16 AM
10:00 - 12:00 |
| (1) |
10:00-10:30 |
Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application |
Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara (Hitachi, Ltd.) |
| (2) |
10:30-11:00 |
A Dynamic SDRAM-Mode Control Scheme for Low-Power Systems |
Seiji Miura, Kazushige Ayukawa (Hitachi,Ltd) |
| (3) |
11:00-11:30 |
Banked Multiported Register File for Highly Parallel Processors |
Ken-ichi Aoyama, Tetsuya Sueyoshi, Koh Johguchi, Moto Maeda, Tetsushi Koide, Hans Juergen Mattausch, Tetsuo Hironaka (Hiroshima Univ.) |
| (4) |
11:30-12:00 |
Architecture of a Multi-Context FPGA Using a Reconfigurable Context Memory |
Masanori Hariyama, Wei Sheng CHONG, Michitaka Kameyama (Tohoku Univ.) |
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12:00-13:00 |
Lunch Break ( 60 min. ) |
Thu, Dec 16 PM
13:00 - 15:00 |
| (5) |
13:00-14:00 |
[Invited Talk]
DRAM Architecture Trend
-- DRAM Architecture Variation in relation to System Requirements -- |
Manabu Ando (Elpida) |
| (6) |
14:00-15:00 |
[Invited Talk]
Inter/Intra-Chip Wireless Interconnection for VLSI using Integrated Antennas |
Takamaro Kikkawa (Hiroshima Univ.) |
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15:00-15:15 |
Break ( 15 min. ) |
Thu, Dec 16 PM
15:15 - 17:15 |
| (7) |
15:15-15:45 |
At-Speed Self-Test LSI for High-Speed Serial Link |
Mamoru Sasaki (Hiroshima Univ.), Kenji Ishimatu (Kumamoto Industrial Research Institute), Morimichi Kanazawa, Shinichi Jintate (Renesas), Hiroyuki Nagahata (Sanyu) |
| (8) |
15:45-16:15 |
A multi-chip vision system with a PWM-based Line parallel interconnection |
Seiji Kameda, Atsushi Iwata (Hiroshima Univ.) |
| (9) |
16:15-16:45 |
Robot Vision System with Parallel Reconfigurable Image Processor |
Takeaki Sugimura, Jun Deguchi, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Atsushi Konno, Hiroyuki Kurino, Masaru Uchiyama, Mitsumasa Koyanagi (Tohoku Univ.) |
| (10) |
16:45-17:15 |
A design of architecture and circuit of data-mining processor |
Akinori Kanasugi, Masao Ohkura, Mitsuhiro Matsumoto (Tokyo Denki Univ.) |
Fri, Dec 17 AM
10:00 - 12:00 |
| (11) |
10:00-10:30 |
A 1V supply successive approximation ADC with rail-to-rail input voltage range |
Yoshihiro Masui, Miho Akagi, Kouichiro Enrin, Takeshi Yoshida, Mamoru Sasaki, Atsushi Iwata (Hiroshima Univ) |
| (12) |
10:30-11:00 |
CMOS Frequency Divider Operating beyond the Upper Frequency Limit of MOSFETs |
Ken Yamamoto, Minoru Fujishima (Tokyo Univ.) |
| (13) |
11:00-11:30 |
0.13-μm CMOS、10-Gbps、16:1 Low-Power Multiplexer |
Ryouta Isozaki, Tadayoshi Enomoto (Chuo Univ.) |
| (14) |
11:30-12:00 |
The Power Reduction of Execution Circuits with Dynamic Power Control Method |
Sinji Itano, Keikiti Tamaru (OUS) |
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12:00-13:00 |
Lunch Break ( 60 min. ) |
Fri, Dec 17 PM
13:00 - 15:00 |
| (15) |
13:00-14:00 |
[Invited Talk]
Self-Timed Data-Driven Processors and their Applications |
Makoto Iwata, Hiroaki Terada (Kochi Univ. of Tech.) |
| (16) |
14:00-14:30 |
Multiple-Valued Current-Mode Differential-Pair Circuit for a High-Speep/High-Reliability Arithmetic VLSI System |
Akira Mochizuki, Takeshi Kitamura, Takahiro Hanyu (Tohoku Univ.) |
| (17) |
14:30-15:00 |
Design and Evaluation of Fine-Grain Field Programmable VLSI Based on Multiple-Valued Source-Coupled Logic |
Haque Mohammad Munirul, Michitaka Kameyama (Tohoku Univ.) |
| Announcement for Speakers |
| General Talk (30) | Each speech will have 20 minutes for presentation and 10 minutes for discussion. |
| Invited Talk (60) | Each speech will have 50 minutes for presentation and 10 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
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| Contact Address |
Masanori Hariyama (Tohoku University)
TEL +81-22-217-7153, FAX +81-22-263-9401
E- :         ecei    |
Last modified: 2004-11-04 23:13:37
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