|
|
| Chair |
|
Toshinori Sueyoshi |
| Vice Chair |
|
Akira Nagoya, Tomomi Sato |
| Secretary |
|
Tetsuo Hironaka, Yuichiro Shibata |
| Assistant |
|
Masahiro Iida |
|
| Conference Date |
Thu, Sep 14, 2006 13:00 - 17:30
Fri, Sep 15, 2006 09:00 - 16:45 |
| Topics |
Reconfigurable Systems, etc. |
| Conference Place |
100th Anniversary Memorial Hall, Kurokami South Campus, Kumamoto University |
| Address |
2-39-1, Kurokami, Kumamoto-shi, 860-8555 Japan |
| Transportation Guide |
http://www.kumamoto-u.ac.jp/e/aboutKU/visitorinfo/location.html |
Contact
Person |
Prof. Morihiro Kuga |
Thu, Sep 14 PM
13:00 - 14:30 |
| (1) |
13:00-13:30 |
Optically Reconfigurable Gate Array with manufacturing defect tolerance |
Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
| (2) |
13:30-14:00 |
Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays |
Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
| (3) |
14:00-14:30 |
An Optically Reconfigurable Gate Array with a liquid crystal hologram |
Yoshiyuki Nakada, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
| |
14:30-14:45 |
Break ( 15 min. ) |
Thu, Sep 14 PM
14:45 - 16:15 |
| (4) |
14:45-15:15 |
A logic design technique using SRAM blocks |
Masayuki Sato, Hiroki Wakamatsu (Ｇｔｉ) |
| (5) |
15:15-15:45 |
Discussion of Memory-LSI Working as Reconfigurable Device |
Masanori Yoshihara, Tetsuo Hironaka (HCU), Masayuki Sato (GTI) |
| (6) |
15:45-16:15 |
Yield enhancement of FPGAs with intra-die variation using multiple configuration data |
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
| |
16:15-16:30 |
Break ( 15 min. ) |
Thu, Sep 14 PM
16:30 - 17:30 |
| (7) |
16:30-17:30 |
[Special Invited Talk]
How to Design FPGAs in a Nanometer Process |
Kazutoshi Kobayashi (Kyoto Univ.) |
| |
- |
|
Fri, Sep 15 AM
09:00 - 10:30 |
| (8) |
09:00-09:30 |
An Implementation of Ant Colony Optimization for the MaTriX Processing Engine |
Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (9) |
09:30-10:00 |
2-dimenstional Kolmogorov-Smirnov test with PROGRAPE-4 and PGR |
Akihiko Ibukiyama, Tsuyoshi Hamada, Naohito Nakasato (RIKEN), Yuichi Okuyama (Aizu Univ.) |
| (10) |
10:00-10:30 |
Numerical Function Generators Based on Polynomial Approximation Suitable for FPGA Implementation |
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School) |
| |
10:30-10:45 |
Break ( 15 min. ) |
Fri, Sep 15 AM
10:45 - 12:15 |
| (11) |
10:45-11:15 |
Context Control Mechanism for Dynamically Reconfigurable Processor MuCCRA |
Hideharu Amano, Yohei Hasegawa, Takuro Nakamura, Takashi Nishimura, Vasutan Tanbunheng (Keio Univ.) |
| (12) |
11:15-11:45 |
PERFORMANCE EVALUATION OF HARDWARE MULTI-PROCESS EXECUTION ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR |
Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano (Keio Univ.) |
| (13) |
11:45-12:15 |
A Parametric Study of Packet-Switched FPGA Overlay Networks |
Daihan Wang, Hiroki Matsutani, Masato Yoshimi (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
| |
12:15-13:30 |
Lunch Break ( 75 min. ) |
Fri, Sep 15 PM
13:30 - 14:30 |
| (14) |
13:30-14:30 |
[Special Invited Talk]
Software Radio
-- Application of Reconfigurable Devices to Wireless Communication -- |
Shinichiro Haruyama (Keio Univ.) |
| |
14:30-14:45 |
Break ( 15 min. ) |
Fri, Sep 15 PM
14:45 - 16:45 |
| (15) |
14:45-15:15 |
Content protection system based on partial reconfiguration of FPGA |
Hiroyuki Yokoyama (KDDI Labs.), Yohei Hori, Kenji Toda (AIST) |
| (16) |
15:15-15:45 |
DESIGN OF IBM PC COMPATIBLE SYSTEM ON AN FPGA AS A PRACTICE EDUCATION |
Shuhei Kinoshita, Shigeru Namiki, Naohiko Shimizu (Tokai Univ.) |
| (17) |
15:45-16:15 |
Implementation of a reconfigurable Java enviroment for embedded systems |
Takayuki Mori, Shinsuke Nino, YoungHun Ko, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
| (18) |
16:15-16:45 |
Self Update Mechanism for Electronic Equipments with Reconfigurable FPGAs. |
Kazuyuki Ushijima, Kazuo Nagata, Hideo Harada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 25 minutes for presentation and 5 minutes for discussion. |
| Special Invited Talk | Each speech will have 50 minutes for presentation and 10 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Masahiro IIDA (Kumamoto Univ.)
E- : ii        -u
TEL: +81-96-342-3649 FAX: +81-96-342-3649 |
Last modified: 2006-07-25 17:08:13
|
Notification: Mail addresses are partially hidden against SPAM.
|