| Paper Abstract and Keywords |
| Presentation |
2006-09-15 11:15
PERFORMANCE EVALUATION OF HARDWARE MULTI-PROCESS EXECUTION ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR
Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano (Keio Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
The hardware multi-process execution is a technique to enhance throughput by dividing reconfigurable devices into several pieces and concurrently execute several processes in the pipelined manner. The hardware multi-process execution on Dynamically Reconfigurable Processor (DRP), which is a coarse grain reconfigurable processor developed by NEC Electronics, is implemented and evaluated with real applications, which can be divided into two categories: a single task like DCT or Viterbi decoder, and multi tasks like a JPEG encoder. A total process for an application is divided into small processes and implemented on a limited area of PE array. Inter-process communication is done through the embedded FIFO. Through the evaluation, the overhead of this modification is not so influenced to the performance, cost and power consumption. When the pipelined execution works well, the throughput is improved almost double. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
DRP / multi-process execution / single-process execution / performance / overhead / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 247, RECONF2006-31, pp. 25-30, Sept. 2006. |
| Paper # |
RECONF2006-31 |
| Date of Issue |
2006-09-08 (RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
RECONF |
| Conference Date |
2006-09-14 - 2006-09-15 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kumamoto Univ. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Reconfigurable Systems, etc. |
| Paper Information |
| Registration To |
RECONF |
| Conference Code |
2006-09-RECONF |
| Language |
English |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
PERFORMANCE EVALUATION OF HARDWARE MULTI-PROCESS EXECUTION ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR |
| Sub Title (in English) |
|
| Keyword(1) |
DRP |
| Keyword(2) |
multi-process execution |
| Keyword(3) |
single-process execution |
| Keyword(4) |
performance |
| Keyword(5) |
overhead |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Vu Manh Tuan |
| 1st Author's Affiliation |
Keio University (Keio Univ.) |
| 2nd Author's Name |
Yohei Hasegawa |
| 2nd Author's Affiliation |
Keio University (Keio Univ.) |
| 3rd Author's Name |
Naohiro Katsura |
| 3rd Author's Affiliation |
Keio University (Keio Univ.) |
| 4th Author's Name |
Hideharu Amano |
| 4th Author's Affiliation |
Keio University (Keio Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2006-09-15 11:15:00 |
| Presentation Time |
30 minutes |
| Registration for |
RECONF |
| Paper # |
RECONF2006-31 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.247 |
| Page |
pp.25-30 |
| #Pages |
6 |
| Date of Issue |
2006-09-08 (RECONF) |