|
|
| Chair |
|
Fumio Horiguchi |
| Vice Chair |
|
Tanemasa Asano |
| Secretary |
|
Morifumi Ohno, Mariko Takayanagi |
| Assistant |
|
Yuichi Matsui |
|
|
|
| Chair |
|
Masao Nakaya |
| Vice Chair |
|
Akira Matsuzawa |
| Secretary |
|
Shinji Miyano, Koji Kai |
| Assistant |
|
Yoshiharu Aimoto, Makoto Nagata |
|
| Conference Date |
Thu, Aug 18, 2005 08:30 - 18:20
Fri, Aug 19, 2005 08:30 - 17:15 |
| Topics |
VLSI Circuits, Device Technologies (High Speed, Low Voltage, Low Power), etc |
| Conference Place |
|
Contact
Person |
0138-34-6226 |
Thu, Aug 18 AM
08:30 - 12:00 |
| (1) |
08:30-08:55 |
A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application |
Yuichiro Murachi (Kobe Univ.), Koji Hamano, Tetsuro Matsuno (Kanazawa Univ.), Junichi Miyakoshi (Kobe Univ.), Masayuki Miyama (Kanazawa Univ.), Masahiko Yoshimoto (Kobe Univ.) |
| (2) |
08:55-09:20 |
An Energy Reduction Method for FFT Circuits in Digital Wireless Communications Using Bitwidth Control |
Masayuki Tokunaga, Kosuke Tarumi, Hiroto Yasuura (Kyushu Univ.) |
| (3) |
09:20-09:45 |
TIS Locking Circuit for Compensating LSI Performance by Temperature Variation |
Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara (Hitachi, Ltd.) |
| (4) |
09:45-10:10 |
A Digital Detector Design For Measuring Gate-Delay Variation |
Ryota Sakamoto, Masanori Muroyama, Kosuke Tarumi, Hiroto Yasuura (Kyushu Univ.) |
| |
10:10-10:25 |
Break ( 15 min. ) |
| (5) |
10:25-11:10 |
[Special Invited Talk]
* |
Makoto Yoshimi (SOITEC Asia) |
| (6) |
11:10-11:35 |
Experimental Study on the Mobility Superiority in (110)-oriented Ultra-thin Body pMOSFETs |
Gen Tsutsui, Masumi Saitoh, Toshiro Hiramoto (Univ. of Tokyo) |
| (7) |
11:35-12:00 |
Variable body-factor FD SOI MOSFET for VTCMOS applications |
Tetsu Ohtou, Toshiharu Nagumo, , Toshiro Hiramoto (Univ. Tokyo) |
| |
12:00-13:00 |
Lunch ( 60 min. ) |
Thu, Aug 18 PM
13:00 - 18:20 |
| (8) |
13:00-13:25 |
Measurement and evaluation of delay variation due to inductive and capacitive coupling noise |
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
| (9) |
13:25-13:50 |
Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits |
Daisuke Kosaka, Makoto Nagata (Kobe Univ.), Yoshitaka Murasaka, Atsushi Iwata (A-R-Tec Corp.) |
| (10) |
13:50-14:15 |
A Test Structure to Analyze (Highly-Doped)/(Lightly-Doped)-Drain in LDD-type CMOSFET |
Takashi Ohzone (Okayama Pref. Univ.), Toshihiro Matsuda (Toyama Pref. Univ.), Kazuhiko Okada, Takayuki Morishita, Kiyotaka Komoku (Okayama Pref. Univ.), Hideyuki Iwata (Toyama Pref. Univ.) |
| |
14:15-14:30 |
Break ( 15 min. ) |
| (11) |
14:30-14:55 |
Delay Modeling and Static Timing Analysis for MTCMOS Circuits |
Naoaki Ohkubo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
| (12) |
14:55-15:20 |
Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes |
Yoshifumi Ikenaga, Masahiro Nomura, Koichi Takeda, Yoetsu Nakazawa (NEC), Yoshiharu Aimoto (NECEL), Yasuhiko Hagihara (NEC) |
| (13) |
15:20-15:45 |
A Low Dynamic Power and Low Leakage Power CMOS Square-Root Circuit |
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) |
| (14) |
15:45-16:10 |
A Low Leakage SRAM Macro with Replica Cell Biasing Scheme |
Osamu Hirabayashi, Yasuhisa Takeyama, Hiroyuki Otake, Keiichi Kushida, Nobuaki Otsuka (Toshiba Corp.) |
| |
16:10-16:20 |
Break ( 10 min. ) |
| (15) |
16:20-18:20 |
SOI; the Trump Card of SOCs in Sub. 50-nm Era
-- Techniques that SOI Conquers Bulk! -- |
Tadayoshi Enomoto (Chuo Univ.), Takakuni Douseki (NTT), Kazutami Arimoto (Renesas), Jiroh Ida (Oki), Takashi Ipposhi (Renesas), Kazuhiko Miki (Toshiba), Masanao Yamaoka (Hitachi), Makoto Yoshimi (SOITEC) |
Fri, Aug 19 AM
08:30 - 12:00 |
| (16) |
08:30-08:55 |
A -90dBc@10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit |
Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa (Matsushita Electric Industrial Co., Ltd) |
| (17) |
08:55-09:20 |
A Low-IF CMOS Single-Chip Bluetooth EDR Transmitter with Digital I/Q Mismatch Trimming Circuit |
Hiroki Ishikuro, Daisuke Miyashita, Taro Shimada, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada, Fumitoshi Hatori (Toshiba) |
| (18) |
09:20-09:45 |
A 106dB audio digital-to-analog converter employing segment flipping technology combined with cascaded dynamic element matching |
Toru Ido, Sonny Ishizuka (TIJ) |
| |
09:45-10:00 |
Break ( 15 min. ) |
| (19) |
10:00-10:45 |
[Special Invited Talk]
HfSiON
-- its high applicability as the alternative gate dielectric based on the high thermal stability and the remaining issue -- |
Akira Nishiyama, Masato Koyama, Yuuichi Kamimuta, Masahiro Koike, Ryosuke Iijima, Takeshi Yamaguchi, Masamichi Suzuki, Tsunehiro Ino, Mizuki Ono (Toshiba) |
| (20) |
10:45-11:10 |
HfSiON Gate Dielectrics Design for Mixed Signal CMOS |
Kenji Kojima, Ryosuke Iijima, Tatsuya Ohguro, Takeshi Watanabe, Mariko Takayanagi, Hisayo S. Momose, Kazunari Ishimaru, Hidemi Ishiuchi (TOSHIBA) |
| (21) |
11:10-11:35 |
Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs |
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo) |
| (22) |
11:35-12:00 |
Gate work-function modulation in SiON/poly-Si gate stacks, and its impact on low power devices
-- Advantage of sub-monolayer Hf at SiON/poly-Si interface -- |
Jiro Yugami (Renesas), Yasuhiro Shimamoto (Hitachi), Masao Inoue, Masaharu Mizutani, Takashi Hayashi, Katsuya Shiga, Fumiko Fujita, Jyunichi Tuchimoto, Yoshikazu Ohno, Masahiro Yoneda (Renesas) |
| |
12:00-13:00 |
Lunch ( 60 min. ) |
Fri, Aug 19 PM
13:00 - 17:15 |
| (23) |
13:00-13:25 |
A Novel Voltage Sensing 1T/2MTJ Cell with Resistance Ratio for Highly Stable and Scalable MRAM |
Masaki Aoki, Hiroshi Iwasa, Yoshihiro Sato (Fujitsu Lab) |
| (24) |
13:25-13:50 |
0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process |
Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi (STARC) |
| (25) |
13:50-14:15 |
A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell |
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
| (26) |
14:15-14:40 |
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories |
Kazuo Otsuga, Hideaki Kurata (Hitachi, Ltd.), Kenji Kozakai, Satoshi Noda (Renesas), Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi (Hitachi, Ltd.) |
| (27) |
14:40-15:05 |
Robust Device Design in FinFET SRAM for hp22nm Technology Node |
Kimitoshi Okano, Tatsuya Ishida, Takahiko Sasaki, Takashi Izumida, Masaki Kondo, Makoto Fujiwara, Nobutoshi Aoki, Satoshi Inaba, Nobuaki Otsuka, Kazunari Ishimaru, Hidemi Ishiuchi (Toshiba) |
| |
15:05-15:15 |
Break ( 10 min. ) |
| (28) |
15:15-17:15 |
High-k; Last Card for the Leakage Currents |
Tadayoshi Enomoto (Chuo Univ.), Mariko Takayanagi (Toshiba), Shigeo Satoh (Fujitu), Koji Nii (Renesas), Akira Nishiyama (Toshiba), ハセ タカシ (NEC), Mototsugu Hamada (Toshiba), Jiro Yugami (Renesas) |
| Contact Address and Latest Schedule Information |
| SDM |
Technical Committee on Silicon Device and Materials (SDM) [Latest Schedule]
|
| Contact Address |
Yasushiro Nishioka (Nihon University, College of Science and Technology)
TEL047-469-6482,FAX047-467-9504
E- :    e   t n-u ,a  cmsk  |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Yoshiharu Aimoto (NEC Electronics)
TEL +81-44-435-1258, FAX +81-44-435-1878
E-:    ai   cel |
Last modified: 2005-07-04 18:51:20
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