| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD, IPSJ-ARC |
2006-06-08
10:00 |
Kanagawa |
|
A Case for Hot-Path-based Branch Prediction
Kosuke Tsuiji, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
[more] |
ICD2006-40
pp.1-6 |
| ICD, IPSJ-ARC |
2006-06-08
10:30 |
Kanagawa |
|
A Low-Power, Reliable Datapath by Reusing Execution Results
Yosuke Hashiguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ) |
[more] |
ICD2006-41
pp.7-12 |
| ICD, IPSJ-ARC |
2006-06-08
11:00 |
Kanagawa |
|
Reducing Energy Consumption of the Dynamic Scheduling Logic by Instruction Grouping
Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo) |
[more] |
ICD2006-42
pp.13-18 |
| ICD, IPSJ-ARC |
2006-06-08
11:30 |
Kanagawa |
|
Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection
Jun Yao, Hajime Shimada (Kyoto Univ.), Yasuhiko Nakashima (NAIST), Shin-ichiro Mori (Fukui Univ.), Shinji Tomita (Kyoto Univ.) |
To reduce the power consumption in mobile processors, a method called Pipeline Stage Unification (PSU) is previously des... [more] |
ICD2006-43
pp.19-24 |
| ICD, IPSJ-ARC |
2006-06-08
13:00 |
Kanagawa |
|
[Special Invited Talk]
The need of a collaboration between the computer architecture and the integrated circuit technology
Hisashige Ando (Fujitsu Ltd.) |
Moor's law continuously gives us more transistors. But, recently, increase in power dissipation becomes the limiting fac... [more] |
ICD2006-44
pp.25-30 |
| ICD, IPSJ-ARC |
2006-06-08
14:00 |
Kanagawa |
|
50% power reduction in H.264/AVC HDTV decoder LSI by dynamic voltage/frequency scaling with elastic pipeline architecture
Kentaro Kawakami (Kobe Univ.), Jun Takemura (Renesas), Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
[more] |
ICD2006-45
pp.31-36 |
| ICD, IPSJ-ARC |
2006-06-08
14:30 |
Kanagawa |
|
Physical Register Access Analysis for Temperature-Aware Microarchitecture
Toshinori Sato (Kyushu Univ.), Yuji Kunitake, Akihiro Chiyonobu (Kyushu Inst. Tech.) |
While the improvements in clock frequency and transistor density have achieved the continuous increase in microprocessor... [more] |
ICD2006-46
pp.37-42 |
| ICD, IPSJ-ARC |
2006-06-08
15:00 |
Kanagawa |
|
Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation
Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka (Kyushu Inst. Tech.), Toshinori Sato (Kyushu Univ.) |
We have investigated a technique for microprocessors, which achieves both high performance and low power. Based on the o... [more] |
ICD2006-47
pp.43-48 |
| ICD, IPSJ-ARC |
2006-06-08
15:30 |
Kanagawa |
|
Design for Testability of Software-Based Self-Test for Processors
Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) |
In this paper, we propose a design for testability method for test programs of software-based self-test using test progr... [more] |
ICD2006-48
pp.49-54 |
| ICD, IPSJ-ARC |
2006-06-08
16:10 |
Kanagawa |
|
[Special Invited Talk]
Discussing the national next-generation supercomputer from the viewpoint of LSI technology and computer architecture
Kazuaki Murakami (Kyushu Univ.) |
[more] |
ICD2006-49
p.55 |
| ICD, IPSJ-ARC |
2006-06-09
09:30 |
Kanagawa |
|
Voltage/Current-Control-Based Low-Power Design of a Multiple-Valued Reconfigurable VLSI
Nobuaki Okada, Haque Mohammad Munirul, Michitaka Kameyama (Tohoku Univ.) |
A new reconfigurable VLSI based on multiple-valued source-coupled logic which has programmable capability is proposed fo... [more] |
ICD2006-50
pp.57-61 |
| ICD, IPSJ-ARC |
2006-06-09
10:00 |
Kanagawa |
|
Dynamically Reconfigurable Architecture for Road Extraction
Sunge Lee, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
[more] |
ICD2006-51
pp.63-67 |
| ICD, IPSJ-ARC |
2006-06-09
10:30 |
Kanagawa |
|
A Reconfigurable Functional Unit for Adaptable Custom Instructions
Hamid Noori (Kyushu Univ.), Farhad Mehdipour (Amirkabir Univ. of Tech.), Kazuaki Murakami, Koji Inoue (Kyushu Univ.), Morteza Saheb Zamani (Amirkabir Univ. of Tech.) |
[more] |
ICD2006-52
pp.69-74 |
| ICD, IPSJ-ARC |
2006-06-09
11:10 |
Kanagawa |
|
[Special Invited Talk]
Architecture and Circuit, How to Collaborate ?
Naoki Nishi (NEC) |
[more] |
ICD2006-53
pp.75-76 |
| ICD, IPSJ-ARC |
2006-06-09
13:00 |
Kanagawa |
|
A Superscalar employing Instruction Decomposition for ARM Architecture
Yasuhiko Nakashima (NAIST) |
[more] |
ICD2006-54
pp.77-82 |
| ICD, IPSJ-ARC |
2006-06-09
13:30 |
Kanagawa |
|
A VLIW Single-Chip Multi-Processor for Multimedia processing
Masahiko Toichi, Atsuhiro Suga, Fumihiko Hayakawa, Shinichiro Tago, Satoshi Imai, Atsushi Tanaka (Fujitsu Lab) |
[more] |
ICD2006-55
pp.83-88 |
| ICD, IPSJ-ARC |
2006-06-09
14:00 |
Kanagawa |
|
Design of a High Performance Vision Processor with Shared Memory Multi-SIMD Architecture
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa (The University of Tokyo) |
For high speed image recognition in real environment, it is a challenge to accelerate a large amount of calculation for ... [more] |
ICD2006-56
pp.89-94 |
| ICD, IPSJ-ARC |
2006-06-09
14:30 |
Kanagawa |
|
Optimal Memory Allocation for Image Processors
Masanori Hariyama (Tohoku Univ.), Yasuhiro Kobayashi (Oyama National College of Tech.), Michitaka Kameyama (Tohoku Univ.) |
[more] |
ICD2006-57
pp.95-100 |
| ICD, IPSJ-ARC |
2006-06-09
15:00 |
Kanagawa |
|
A Virtual-Channel Free Mapping for On-Chip Torus Networks
Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
[more] |
ICD2006-58
pp.101-106 |
| ICD, IPSJ-ARC |
2006-06-09
15:45 |
Kanagawa |
|
[Panel Discussion]
How do we create combining architecture and integrated circuits?
Kunio Uchiyama (Hitachi, Ltd.,) |
(To be available after the conference date) [more] |
ICD2006-59
p.107 |
|