| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| RECONF |
2005-05-12
09:30 |
Kyoto |
Kyoto University |
A Reconfigurable Embedded Decompressor for LSI Testing
Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
The problem of the increase in test data size for large-scale curcuits has developed.
In order to solve this problem, s... [more] |
RECONF2005-1
pp.1-6 |
| RECONF |
2005-05-12
10:00 |
Kyoto |
Kyoto University |
Development of clustering tool to reduce area of chip and delay
Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
In this paper,we present a clustering technique for area and delay reduction in clustered FPGAs.
This technique uses tw... [more] |
RECONF2005-2
pp.7-12 |
| RECONF |
2005-05-12
10:30 |
Kyoto |
Kyoto University |
Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
The dynamic reconfigurable processor is a device that can change interconnections between processor elements and process... [more] |
RECONF2005-3
pp.13-18 |
| RECONF |
2005-05-12
11:00 |
Kyoto |
Kyoto University |
Implementation of an SMT Processor and its Reconfigurable Cache with FPGA
Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo (Tokyo University of Agriculture and Technology) |
Recently, it becomes possible to implement a large-scale processor
due to speed-up and large-scale integrity of an FPG... [more] |
RECONF2005-4
pp.19-24 |
| RECONF |
2005-05-12
11:30 |
Kyoto |
Kyoto University |
Improvement of Signature-based Phase Detection and its Application to Power Reduction in Caches
Yuya Ueno, Luong D. Hung (Tokyo Univ.), Masanori Takada, Daisuke Tashiro (Hitachi), Shuichi Sakai (Tokyo Univ.) |
[more] |
RECONF2005-5
pp.25-30 |
| RECONF |
2005-05-12
13:00 |
Kyoto |
Kyoto University |
[Invited Talk]
A general view on VLSI design methodology
Yukihiro Nakamura (Kyoto Univ.) |
[more] |
RECONF2005-6
pp.31-35 |
| RECONF |
2005-05-12
14:00 |
Kyoto |
Kyoto University |
Design of a Heap-tree Based Scalable Stochastic Biochemical Simulator on an FPGA
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
[more] |
RECONF2005-7
pp.37-42 |
| RECONF |
2005-05-12
14:30 |
Kyoto |
Kyoto University |
Scheduling of Rate Law Functions for an FPGA-based Biochemical Simulator
Naoki Iwanaga, Yuichiro Shibata (Nagasaki Univ.), Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano (Keio Univ), Akira Funahashi, Noriko Hiroi, Hiroaki Kitano (JST), Kiyoshi Oguri (Nagasaki Univ.) |
A reconfigurable biochemical simulator solving ordinary differential
equations has received attention as a personal hig... [more] |
RECONF2005-8
pp.43-48 |
| RECONF |
2005-05-12
15:00 |
Kyoto |
Kyoto University |
Implementation and Evaluation of Numerical Integrators on ReCSiP
Yasunori Osana, Masato Yoshimi, Yow Iwaoka (Keio Univ.), Akira Funahashi, Noriko Hiroi (ERATO-SORST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (ERATO-SORST), Hideharu Amano (Keio Univ.) |
[more] |
RECONF2005-9
pp.49-54 |
| RECONF |
2005-05-12
15:45 |
Kyoto |
Kyoto University |
Analyses of Operating Speed and Power Consumption in Flex Power FPGA
-- From Circuit Level To Chip Level --
Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
Flex Power FPGA can flexibly control the operating speed and power consumption by the threshold voltage of transistor. T... [more] |
RECONF2005-10
pp.55-60 |
| RECONF |
2005-05-12
16:15 |
Kyoto |
Kyoto University |
Area Overhead Estimation for Vth Control in Flex Power FPGA
Takashi Kawanami, Masakazu Hioki (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed and low power consumption by controling threshol... [more] |
RECONF2005-11
pp.61-66 |
| RECONF |
2005-05-12
16:45 |
Kyoto |
Kyoto University |
Reducing the Delay by Using the Small-World Network Structure
Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
The logic density of FPGA has imploved rapidly. However, as for deep sub-micron processes, the wire delay accounts for a... [more] |
RECONF2005-12
pp.67-72 |
| RECONF |
2005-05-12
17:15 |
Kyoto |
Kyoto University |
Code Scheduling in Consideration of Place and Wire in Back End Compiler for PARS
Ryuji Hada, Takeshi Takeuchi, Takeshi Fukuda, Kazuya Tanigawa, Tetsuo Hironaka (HCU) |
We have proposed a reconfigurable PARS architecture for general-purpose,and developing the PARS Compiler.We are developi... [more] |
RECONF2005-13
pp.73-78 |
| RECONF |
2005-05-12
17:45 |
Kyoto |
Kyoto University |
A Simulation Platform for Evaluating Granularity of Self-Reconfigurable Device
Shin'ichi Kouyama, Futoshi Morie, Kentaro Nakahara (Kyoto Univ.), Tomonori Izumi (Ritsumeikan Univ.), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
[more] |
RECONF2005-14
pp.79-84 |
| RECONF |
2005-05-13
09:00 |
Kyoto |
Kyoto University |
Development of a testbed RCPII to evaluate effects of a real environment for a reconfigurable computing
Kosei Shimoo, Akira Yamawaki, Masahiko Iwane (KIT) |
To familiarize reconfigurable computing, it is important to improve system using the result of evaluating including beha... [more] |
RECONF2005-15
pp.1-5 |
| RECONF |
2005-05-13
09:30 |
Kyoto |
Kyoto University |
An implementation of number-plate recognition algorithm on reconfigurable system
Takamasa Kanamori, Shizuto Fukuda (Keio Univ.), Yoshiaki Ajioka (Ecchandes), Masatoshi Arai (CalsonicKansei), Shinya Hashimoto (MEITEC), Hideharu Amano (Keio Univ.) |
[more] |
RECONF2005-16
pp.7-11 |
| RECONF |
2005-05-13
10:00 |
Kyoto |
Kyoto University |
Experiment on number recognition for parallel operation
Masatoshi Arai (CalsonicKansei), Shinya Hashimoto (MEITEC), Yoshiaki Ajioka (Ecchandes), Takamasa Kanamori, Shizuto Fukuda, Hideharu Amano (Keio Univ.) |
Important matters of an image processing system carried on a car different from other image processing systems are (1) r... [more] |
RECONF2005-17
pp.13-17 |
| RECONF |
2005-05-13
10:30 |
Kyoto |
Kyoto University |
Reconfigurable 3D-FFT processor
Tohru Sasaki (APM), Umpei Nagashima (AIST) |
(To be available after the conference date) [more] |
RECONF2005-18
pp.19-23 |
| RECONF |
2005-05-13
11:00 |
Kyoto |
Kyoto University |
Data-Supplying Subsystem for the Parallel Reconfigurable Image Processing System
Akiyoshi Wakatani (Konan Univ.), Hiroshi Kadota (Kyushu Univ.) |
[more] |
RECONF2005-19
pp.25-30 |
| RECONF |
2005-05-13
11:30 |
Kyoto |
Kyoto University |
Developing a parallel reconfigurable system for physics computations
Tsuyoshi Hamada, Naohito Nakasato (RIKEN) |
We have developped PROGRAPE-3P1, a reconfigurable system for particle based simulations. The peak spead of PROGRAPE-3P1 ... [more] |
RECONF2005-20
pp.31-36 |