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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2011)
Search Results: Keywords 'from:2011-05-12 to:2011-05-12'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2011-05-12 10:20 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Resource Sharing in FPGA and Implementation of Face-Angle Detection Algorithm using Impulse C Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic), Hideharu Amano (Keio Univ.)  RECONF2011-1 |
Most of systems developed to prevent inattentive driving utilize a visible light camera with various processing algorith... [more] | RECONF2011-1 pp.1-6 |
| RECONF | 2011-05-12 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Pattern Compression of FAST Corner Detection and its FPGA Implementation Keisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2011-2 |
[more] | RECONF2011-2 pp.7-12 |
| RECONF | 2011-05-12 11:10 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | An Implementation of Mean Shift Filter on FPGA Dang Ba Khac Trieu, Tsutomu Maruyama (University of Tsukuba) RECONF2011-3 |
[more] | RECONF2011-3 pp.13-18 |
| RECONF | 2011-05-12 11:35 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | A real-time stereo vision system using a tree-structured dynamic programming on FPGA Minxi Jin, Tsutomu Maruyama (Tsukuba Univ.) RECONF2011-4 |
[more] | RECONF2011-4 pp.19-24 |
| RECONF | 2011-05-12 13:30 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Context Synchronization Method for Reliable Softcore Processor System Makoto Fujino, Noritaka Kai, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-5 |
SRAM-based FPGAs are vulnerable to a SEU, which is induced by radiation effect. The SEU's effects on configuration mem... [more] |
RECONF2011-5 pp.25-30 |
| RECONF | 2011-05-12 13:55 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Evaluation of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures Hiroaki Konoura (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2011-6 |
For wear-out failures, some fault avoidance methods on dynamically reconfigurable devices have been discussed. In order... [more] | RECONF2011-6 pp.31-36 |
| RECONF | 2011-05-12 14:20 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation Tadashi Okabe (TIRI) RECONF2011-7 |
Asynchronous circuit design can solved many problems related to power consumption , EMI , clock skew and so on . Recentl... [more] | RECONF2011-7 pp.37-42 |
| RECONF | 2011-05-12 15:00 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Design and Implementation of a Portable Framework for PCI Express Interface Shoichi Igarashi, Ryuhei Morita, Yuichi Okuyama (Univ. of Aizu), Tsuyoshi Hamada (Nagasaki Univ.), Junji Kitamichi, Kenichi Kuroda (Univ. of Aizu) RECONF2011-8 |
In this paper, we propose a portable framework for PCI Express interface. The proposed framework provides DMA transfer a... [more] | RECONF2011-8 pp.43-48 |
| RECONF | 2011-05-12 15:25 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Development of Wireless Video Transmission Equipment in 5GHz MIMO-OFDM Using FPGA Jun Takizawa, Takaya Kaji, Shingo Yoshizawa (Hokkaido Univ.), Takashi Gunji, Morio Tawarayama (Mitubishi Denki Tokki System), Yoshikazu Miyanaga (Hokkaido Univ.) RECONF2011-9 |
MIMO-OFDM enables high-speed wireless communication, and is employed in IEEE802.11n and IEEE802.11ac. We developed a 2x2... [more] | RECONF2011-9 pp.49-54 |
| RECONF | 2011-05-12 15:50 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | A Virus Scanning Engine Using a 4IGU Emulator and an MPU Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2011-10 |
This paper shows a virus scanning system using two-stage matching. In the first stage, a hardware filter quickly detect... [more] |
RECONF2011-10 pp.55-60 |
| RECONF | 2011-05-12 16:30 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | [Invited Talk]
ERATO MINATO Discrete Structure Manipulation System Project and Current Work on System Design Area Shin-ichi Minato (Hokkaido Univ.) RECONF2011-11 |
[more] | RECONF2011-11 pp.61-66 |
| RECONF | 2011-05-13 09:15 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | * Akira Fukui, Masahiro Fujita (Tokyo University) RECONF2011-12 |
Smith-Waterman Algorithm is utilized for alignment of DNA and protein sequences. When an un- known sample of DNA or pro... [more] |
RECONF2011-12 pp.67-72 |
| RECONF | 2011-05-13 09:40 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation of Out-Of-Order Execution System for Acceleration of Surface Integral in FaSTAR Takayuki Akamine, Kenta Inakagata (Keio Univ.), Yasunori Osana (Ryukyu Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) RECONF2011-13 |
CFD is an important tool to design aircraft components. FaSTAR is one of the most recent CFD program package with variou... [more] | RECONF2011-13 pp.73-78 |
| RECONF | 2011-05-13 10:05 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Evaluation of Scalable Streaming Array for High-Performance Stencil Computation with Low Memory Bandwidth Kentaro Sano (Tohoku Univ.), Yoshiaki Hatsuda (Kobo Co. Ltd), Yoshiaki Kono, Satoru Yamamoto (Tohoku Univ.) RECONF2011-14 |
[more] | RECONF2011-14 pp.79-84 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
| RECONF | 2011-05-13 11:10 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Implementation and Evaluation of a low power accelerator SLD-2 Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16 |
Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] | RECONF2011-16 pp.91-96 |
| RECONF | 2011-05-13 11:35 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Power Consumption Evaluation of a Dynamically Reconfigurable Multi-cryptoprocessor on Virtex-5 FPGA Yohei Hori, Toshihiro Katashita, Akashi Satoh (AIST) RECONF2011-17 |
[more] | RECONF2011-17 pp.97-102 |
| RECONF | 2011-05-13 13:30 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | A Implementation of Programmable Re-Ordering Unit for Array Processor Tomoyoshi Kobori, Nozomi Ishihara, Katsutoshi Seki, Masao Ikekawa (NEC) RECONF2011-18 |
We present a novel re-ordering unit architecture for array processor. In novel re-ordering unit, memory architecture is ... [more] | RECONF2011-18 pp.103-108 |
| RECONF | 2011-05-13 13:55 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | A Homogeneous Routing Architecture for Efficient FPGA Design Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-19 |
In previous work, we have designed a prototype chip of island-style FPGA architecture. This architecture has very comple... [more] | RECONF2011-19 pp.109-114 |
| RECONF | 2011-05-13 14:20 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | A Novel Abridged Adaptive LUT Architecture with Few Configulation Memories Ken Taura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-20 |
Look-up tables(LUTs)are adopted for field programmable gate arrays(FPGAs)as programmable logic cells. N-input LUTs can i... [more] | RECONF2011-20 pp.115-120 |
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