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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2019)

Search Results: Keywords 'from:2019-05-15 to:2019-05-15'
[Go to Official VLD Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2019-05-15
13:55		 Tokyo Ookayama Campus, Tokyo Institute of Technology A study on replica topology and temperature assignment for Ising-Model based Solver via Parallel Tempering
Akira Dan, Takashi Sato (Kyoto Univ.) VLD2019-1		 Ising-model based solver {¥sato{is gaining increasing}} attention
{¥sato{for its efficiency in}} finding approximate s... [more]		 VLD2019-1
pp.7-12
VLD, IPSJ-SLDM 2019-05-15
14:20		 Tokyo Ookayama Campus, Tokyo Institute of Technology Approximate Computing Technique Using Memoization and Simplified Multiplication
Yoshinori Ono, Kimiyoshi Usami (SIT) VLD2019-2		 In embedded systems, approximate computing can strongly promote reduction of execution time and energy consumption in ex... [more] VLD2019-2
pp.13-18
VLD, IPSJ-SLDM 2019-05-15
15:00		 Tokyo Ookayama Campus, Tokyo Institute of Technology Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory
Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2019-3		  [more] VLD2019-3
pp.19-23
VLD, IPSJ-SLDM 2019-05-15
15:25		 Tokyo Ookayama Campus, Tokyo Institute of Technology SRAM-Based Synthesis for Multi-Output Gates
Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-4		 Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation... [more] VLD2019-4
pp.25-30
VLD, IPSJ-SLDM 2019-05-15
15:50		 Tokyo Ookayama Campus, Tokyo Institute of Technology The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process
Hideharu Amano, Hideto Kayashima, Tsunaaki Shidei, Takuya Kojima (Keio Univ.) VLD2019-5		 (To be available after the conference date) [more] VLD2019-5
pp.31-36
VLD, IPSJ-SLDM 2019-05-15
16:30		 Tokyo Ookayama Campus, Tokyo Institute of Technology [Invited Talk] Viaswitch FPGA for Energy Efficient Computing
Masanori Hashimoto (Osaka Univ.) VLD2019-6		  [more] VLD2019-6
pp.37-41
 Results 1 - 6 of 6  /   
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