| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
13:30 |
Fukuoka |
Kitakyushu International Conference Center |
[Fellow Memorial Lecture]
Layout CAD and DFM
-- Beginning and Maturity --
Takashi Mitsuhashi (Cadence Japan) |
The auther had an opportunity to be engaged in development of VLSI layout design automation, and automation of design ve... [more] |
VLD2005-54 ICD2005-149 DC2005-31
pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
14:40 |
Fukuoka |
Kitakyushu International Conference Center |
40-Gbps 4:1 MUX/1:4 DEMUX in 90-nm standard CMOS technology
Kouichi Kanda, Daisuke Yamazaki, Takuji Yamamoto, Minoru Horinaka, Junji Ogawa, Hirotaka Tamura, Hiroyuki Onodera (Fujitsu Labs.) |
[more] |
VLD2005-55 ICD2005-150 DC2005-32
pp.7-14 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
15:05 |
Fukuoka |
Kitakyushu International Conference Center |
Enhancement of an Angular Position Error Measurement Circuit for Rotary Encoders
Teruo Tamama, , Tadashi Masuda (SIST) |
[more] |
VLD2005-56 ICD2005-151 DC2005-33
pp.15-20 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
15:30 |
Fukuoka |
Kitakyushu International Conference Center |
Low Power Design for IEEE 802.11 WLAN at the Medium Access Control Layer
EL Bourichi Adil, Hiroto Yasuura (Kyushu Univ.) |
[more] |
VLD2005-57 ICD2005-152 DC2005-34
pp.21-24 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
16:10 |
Fukuoka |
Kitakyushu International Conference Center |
Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
Masao Morimoto, Makoto Nagata (Kobe Univ.), Kazuo Taki |
This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The te... [more] |
VLD2005-58 ICD2005-153 DC2005-35
pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
16:35 |
Fukuoka |
Kitakyushu International Conference Center |
A Discussion about Timing Signal Design Considering Delay Variation
Masashi Imai, Kouichi Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations become extremely
large. There are many factors that cause delay varia... [more] |
VLD2005-59 ICD2005-154 DC2005-36
pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-11-30
17:00 |
Fukuoka |
Kitakyushu International Conference Center |
Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. Tokyo) |
As the VLSI technology advances, delay variations will become more serious.
Delay insensitive asynchronous dual-rail ci... [more] |
VLD2005-60 ICD2005-155 DC2005-37
pp.37-42 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
09:30 |
Fukuoka |
Kitakyushu International Conference Center |
Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure
Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable ga... [more] |
VLD2005-61 ICD2005-156 DC2005-38
pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
09:55 |
Fukuoka |
Kitakyushu International Conference Center |
A equidistant transition circuit for detecting path-delay faults
Hyonsu Cho, Takeo Yoshida (Univ. of the Ryukyus) |
In this paper, we propose a equidistant transition circuit for detecting path delay faults. A value of each register in ... [more] |
VLD2005-62 ICD2005-157 DC2005-39
pp.7-12 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
10:20 |
Fukuoka |
Kitakyushu International Conference Center |
Reconfigurable Wrapper Design for Multi Clock Domain Cores Under Power Constraints
Yu Tanaka, Tomokazu Yoneda, Hideo Fujiwara (NAIST) |
This paper presents a re-configurable wrapper design for scan-designed multi-clock domain cores in system-on-chips. The ... [more] |
VLD2005-63 ICD2005-158 DC2005-40
pp.13-18 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
11:00 |
Fukuoka |
Kitakyushu International Conference Center |
Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule
Mineo Kaneko (JAIST) |
[more] |
VLD2005-64 ICD2005-159 DC2005-41
pp.19-24 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
11:25 |
Fukuoka |
Kitakyushu International Conference Center |
A Consideration of Chaining methods on Behavioral Synthesis
Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) |
In Behavioral Synthesis, operation chaining is one of the e±cient techniques to reduce the number of
control steps. Alm... [more] |
VLD2005-65 ICD2005-160 DC2005-42
pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
11:50 |
Fukuoka |
Kitakyushu International Conference Center |
A High-level Synthesis Algorithm Based on Floorplans for Distributed/Shared-Register Architectures
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
[more] |
VLD2005-66 ICD2005-161 DC2005-43
pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
13:30 |
Fukuoka |
Kitakyushu International Conference Center |
Pipelined Bipartite Modular Multiplication
Marcelo E. Kaihara, Naofumi Takagi (Nagoya Univ.) |
[more] |
VLD2005-67 ICD2005-162 DC2005-44
pp.37-42 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
13:55 |
Fukuoka |
Kitakyushu International Conference Center |
no title
Keita Okubo, noname, noname, Takashi Kambe (noname) |
In the design of the arithmetic circuit for the embedded system, it is necessary to consider optimization of circuit sca... [more] |
VLD2005-68 ICD2005-163 DC2005-45
pp.43-48 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
14:20 |
Fukuoka |
Kitakyushu International Conference Center |
Consideration on Delay Estimation Methods for Prefix Graphs
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
Prefix graph is an abstract representation of a parallel prefix adder and used to compare characteristics of various typ... [more] |
VLD2005-69 ICD2005-164 DC2005-46
pp.49-54 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
14:45 |
Fukuoka |
Kitakyushu International Conference Center |
Comparison of power consumption by form of adders
Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT) |
We reported "Comparison of power consumption, area and speed by form of adders " at the VLSI design technical research m... [more] |
VLD2005-70 ICD2005-165 DC2005-47
pp.55-59 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
15:25 |
Fukuoka |
Kitakyushu International Conference Center |
A Study of the Model and the Accuracy of Statistical Timing Analysis
Izumi Nitta, Katsumi Homma, Toshiyuki Shibuya (Fujitsu Lab.) |
[more] |
VLD2005-71 ICD2005-166 DC2005-48
pp.61-66 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
15:50 |
Fukuoka |
Kitakyushu International Conference Center |
Fast Interconnect Delay Estimation with Considering Inductance Based on Multiple Regression Analysis
Kosei Suzuki, Marta D.Anwar, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
In recent DSM (Deep SubMicron) technology, we need to take some important points, such as floorplaning, interconnect res... [more] |
VLD2005-72 ICD2005-167 DC2005-49
pp.67-72 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
16:15 |
Fukuoka |
Kitakyushu International Conference Center |
Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect
Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) |
[more] |
VLD2005-73 ICD2005-168 DC2005-50
pp.73-78 |