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|
| Chair |
|
Yoshiki Yamaguchi (Tsukuba Univ.) |
| Vice Chair |
|
Yasushi Inoguchi (JAIST), Tomonori Izumi (Ritsumeikan Univ.) |
| Secretary |
|
Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.) |
| Assistant |
|
Yukitaka Takemura (INTEL), Yasunori Osana (Kumamoto Univ.) |
|
| Conference Date |
Thu, Sep 14, 2023 13:40 - 17:00
Fri, Sep 15, 2023 09:30 - 15:05 |
| Topics |
Reconfigurable system, etc. |
| Conference Place |
Koganei Campus, Tokyo University of Agriculture and Technology |
| Address |
184-8588 2-24-16 Nakacho Koganei-shi Tokyo Japan |
| Transportation Guide |
https://www.tuat.ac.jp/en/outline/overview/access/ |
Contact
Person |
Division of Advanced Information Technology and Computer Science Hironori Nakajo |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF. |
Thu, Sep 14 PM
13:30 - |
| |
13:30-13:40 |
( 10 min. ) |
Thu, Sep 14 PM
13:40 - 14:40 |
| (1) |
13:40-14:40 |
[Invited Talk]
Virtual reconfigurable system by software |
Shuichi Takada (ArchiTek) |
| |
14:40-15:00 |
Break ( 20 min. ) |
Thu, Sep 14 PM
15:00 - 15:50 |
| (2) |
15:00-15:25 |
Monitoring system for optically reconfigurable gate arrays under radiation environments  RECONF2023-19 |
Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
| (3) |
15:25-15:50 |
Implementation of a sequential circuit onto an optically reconfigurable gate array VLSI without any crystal oscillator RECONF2023-20 |
Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
| |
15:50-16:10 |
Break ( 20 min. ) |
Thu, Sep 14 PM Lightning Talk
16:10 - 17:00 |
| (4) |
16:10-16:20 |
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA) RECONF2023-21 |
Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) |
| (5) |
16:20-16:30 |
Integrating RISC-V Vector Extension and SMT for Embedded AI Workloads RECONF2023-22 |
Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) |
| (6) |
16:30-16:40 |
RECONF2023-23 |
|
| (7) |
16:40-16:50 |
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism RECONF2023-24 |
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) |
| (8) |
16:50-17:00 |
Construction of Visualization Environment for CGRA Operation Verification RECONF2023-25 |
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT) |
Fri, Sep 15 AM
09:30 - 10:45 |
| (1) |
09:30-09:55 |
RECONF2023-26 |
|
| (2) |
09:55-10:20 |
SATA burst data transfer pattern of state vector simulator RECONF2023-27 |
Hideharu Amano, Wei Kaijie (Keio Univ.), Ryohei Nisawa (Univ. of Tsukuba), Takefumi Miyoshi (Wasalabo), Yoshiki Yamaguchi (Univ. of Tsukuba) |
| (3) |
10:20-10:45 |
* RECONF2023-28 |
Shintaro Kawasaki, Mizuki Ito, Yoshiki Yamaguchi () |
Fri, Sep 15 PM
10:45 - 12:15 |
| (4) |
10:45-12:15 |
|
| |
12:15-13:25 |
Break ( 70 min. ) |
Fri, Sep 15 PM
13:25 - 15:05 |
| (5) |
13:25-13:50 |
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer RECONF2023-29 |
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) |
| (6) |
13:50-14:15 |
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA) RECONF2023-30 |
Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) |
| (7) |
14:15-14:40 |
Library Development for RISC-V FPGA SoCs RECONF2023-31 |
Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) |
| (8) |
14:40-15:05 |
On the FPGA Implementation of a Lightweight Neural Network for Point Clouds RECONF2023-32 |
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
Fri, Sep 15 PM
15:05 - 15:05 |
| |
15:05-15:15 |
( 10 min. ) |
| |
15:15-15:20 |
( 5 min. ) |
Fri, Sep 15 PM
15:30 - 15:20 |
| |
15:30-17:00 |
( 90 min. ) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Last modified: 2023-09-11 11:29:49
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