Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2023-09-14 16:40
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24
Abstract (in Japanese) (See Japanese page) 
(in English) Vector processors can load lots of data and perform operations in parallel.
The Vector Register Sharing Mechanism, proposed by our laboratory for faster data transfer to accelerators, directly connects accelerators to vector registers in a vector processor instead of memory.
In this paper, we verify the effectiveness of the V.R. Sharing Mechanism by simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / Vector Architecture / Hardware Acceleration / / / / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 191, RECONF2023-24, pp. 18-19, Sept. 2023.
Paper # RECONF2023-24 
Date of Issue 2023-09-07 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2023-24

Conference Information
Committee RECONF  
Conference Date 2023-09-14 - 2023-09-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Tokyo University of Agriculture and Technology Koganei campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable system, etc. 
Paper Information
Registration To RECONF 
Conference Code 2023-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) Vector Architecture  
Keyword(3) Hardware Acceleration  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Go Akamatsu  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Tomoaki Tanaka  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Kiyofumi Tanaka  
3rd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
4th Author's Name Yasunori Osana  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Takefumi Miyoshi  
5th Author's Affiliation Wasalabo, LLC (Wasalabo)
6th Author's Name Jubee Tada  
6th Author's Affiliation Yamagata University (Yamagata Univ.)
7th Author's Name Hironori Nakajo  
7th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2023-09-14 16:40:00 
Presentation Time 10 minutes 
Registration for RECONF 
Paper # RECONF2023-24 
Volume (vol) vol.123 
Number (no) no.191 
Page pp.18-19 
#Pages 2 
Date of Issue 2023-09-07 (RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan