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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2011-09-26
10:45		 Aichi Nagoya Univ. Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1.
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications) RECONF2011-22		 CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] RECONF2011-22
pp.1-6
RECONF 2011-05-13
10:45		 Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) Optimization of Application Programs of SLD-1 : A Low Power Accelarator
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15		 SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] RECONF2011-15
pp.85-90
RECONF 2011-05-13
11:10		 Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) Implementation and Evaluation of a low power accelerator SLD-2
Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2011-16		 Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobil... [more] RECONF2011-16
pp.91-96
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
14:10		 Kanagawa Keio Univ (Hiyoshi Campus) Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61		 This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] VLD2010-92 CPSY2010-47 RECONF2010-61
pp.49-54
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
14:50		 Kanagawa Keio Univ (Hiyoshi Campus) Silent Large Datapath : A Ultra Low Power Accelarater
Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78		 Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded
systems. By using a... [more]		 VLD2010-109 CPSY2010-64 RECONF2010-78
pp.169-174
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
15:10		 Kanagawa Keio Univ (Hiyoshi Campus) Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79		 Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] VLD2010-110 CPSY2010-65 RECONF2010-79
pp.175-180
RECONF 2010-09-17
11:00		 Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Removing context memory from Multi-context Dynamically Reconfigurable Processors
Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.) RECONF2010-34		 Although context memory or configuration cache is a key mechanism for quick dyna
mic
reconfiguration of multi-context ... [more]		 RECONF2010-34
pp.97-102
RECONF 2010-09-17
11:25		 Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration
Masayuki Kimura, Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2010-35		  [more] RECONF2010-35
pp.103-108
RECONF 2010-05-13
14:55		 Nagasaki   A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array
Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2010-4		 Recently, since a mobile device is required to provide various functions,
a lot of specialized hardware modules must be... [more]		 RECONF2010-4
pp.19-24
 Results 1 - 9 of 9  /   
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