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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS, ICD 2024-02-29
16:45
Okinawa
(Primary: On-site, Secondary: Online)
[Memorial Lecture] Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Tech) VLD2023-119 HWS2023-79 ICD2023-108
(To be available after the conference date) [more] VLD2023-119 HWS2023-79 ICD2023-108
pp.101-106
RECONF 2023-08-04
14:30
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
Pianissimo: A Sub-mW Class DNN Accelerator For Adaptive Inference at Edge
Junnosuke Suzuki, Mari Yasunaga, Angel Lopez Garcia-Arias, Yasuyuki Okoshi, Shungo Kumazawa (Tokyo Tech), Kota Ando (Hokkaido Univ.), Kazushi Kawamura, Thiem Van Chu, Masato Motomura (Tokyo Tech) RECONF2023-14
(To be available after the conference date) [more] RECONF2023-14
pp.1-6
NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] 2023-06-29
13:55
Okinawa OIST Conference Center
(Primary: On-site, Secondary: Online)
NC2023-2 IBISML2023-2 (To be available after the conference date) [more] NC2023-2 IBISML2023-2
pp.9-16
PRMU, IPSJ-CVIM 2023-05-19
15:10
Aichi
(Primary: On-site, Secondary: Online)
Ultralight Object Detection Neural Network based on Strong Lottery Ticket Hypothesis
Hikari Otsuka, Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura (Tokyo Tech) PRMU2023-11
 [more] PRMU2023-11
pp.57-61
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
15:15
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
A Study of Sparse Matrix Multiplication Accelerator
Yuta Nagahara (Tokyo Tech), Kota Ando (Hokkaido University), Kazushi Kawamura, Jaehoon Yu, Masato Motomura, Thiem Van Chu (Tokyo Tech) CPSY2022-11 DC2022-11
 [more] CPSY2022-11 DC2022-11
pp.59-64
SIS, IPSJ-AVM 2021-06-24
13:25
Online Online A Study of Ensemble Learning for Randomly Weighted Neural Network
Yasuyuki Okoshi, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu (Tokyo Tech) SIS2021-7
Recent research on deep learning shows the possibility of building neural networks by learning connection existences ins... [more] SIS2021-7
pp.37-42
RECONF 2021-06-08
14:10
Online Online RECONF2021-2 (To be available after the conference date) [more] RECONF2021-2
pp.2-7
RECONF 2021-06-08
15:00
Online Online RECONF2021-4 (To be available after the conference date) [more] RECONF2021-4
pp.14-19
RECONF 2021-06-08
16:35
Online Online RECONF2021-7 (To be available after the conference date) [more] RECONF2021-7
pp.32-37
CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] 2017-01-24
17:45
Kanagawa Hiyoshi Campus, Keio Univ. Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs
Thiem Van Chu, Kenji Kise (Tokyo Tech) VLD2016-93 CPSY2016-129 RECONF2016-74
 [more] VLD2016-93 CPSY2016-129 RECONF2016-74
pp.153-158
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
15:05
Osaka Ritsumeikan University, Osaka Ibaraki Campus A Novel Merge Network for FPGA Sorting Accelerators
Makoto Saitoh, Susumu Mashimo, Thiem Van Chu, Kenji Kise (Tokyotech) RECONF2016-42
 [more] RECONF2016-42
pp.13-18
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2016-08-09
15:00
Nagano Kissei-Bunka-Hall (Matsumoto) A Fast Emulation System for Fat-Tree-Based Network-on-Chips
Thiem Van Chu, Kenji Kise (Tokyo Tech) CPSY2016-24
(To be available after the conference date) [more] CPSY2016-24
pp.161-166
RECONF 2014-09-18
15:45
Hiroshima   Challenge for Ultrafast 10K-Node NoC emulation on FPGA
Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) RECONF2014-21
With thousands of cores in the near future NoC architectures, the simulation time is a serious problem that makes archit... [more] RECONF2014-21
pp.23-28
 Results 1 - 13 of 13  /   
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