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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 14:15 |
Miyagi | Hierarchical GALS system based on ring segmented bus architecture Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.)  VLD2014-63 ICD2014-56 IE2014-42 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed as an asynchronous bus a... [more] | VLD2014-63 ICD2014-56 IE2014-42 pp.19-24 |
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| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 15:10 |
Hokkaido | Hokkaido University | A distributed asynchronous arbiter for ring segmented bus type GALS systems Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] | CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 pp.237-242 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| VLD | 2009-03-12 14:50 |
Okinawa | A ring segmented bus architrcture for Globally Asynchronous Locally Synchronous System Masafumi Kondo, Yoichiro Sato (Okayama Prefectural Univ), Kazuyuki Tashiro (FUJITSU TEN), Tomoyuki Yokogawa, Michiyoshi Hayase (Okayama Prefectural Univ) VLD2008-149 |
Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems. Several archit... [more] |
VLD2008-149 pp.135-140 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 12:20 |
Kanagawa | A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79 |
In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] | VLD2008-115 CPSY2008-77 RECONF2008-79 pp.141-146 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 14:45 |
Kanagawa | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | VLD2008-120 CPSY2008-82 RECONF2008-84 pp.171-176 |
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| ICD | 2005-12-15 11:20 |
Kochi | Scalable Bus Interface for HSDPA Co-processor Extension Toshiki Takeuchi, Hiroyuki Igura (NEC), Takeshi Hashimoto (NECEL), Soichi Tsumura, Naoki Nishi (NEC) |
This paper presents a scalable bus developed for HSDPA co-processor extension of W-CDMA digital baseband processors. The... [more] | ICD2005-184 pp.7-11 |
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| IE, SIP, ICD, IPSJ-SLDM | 2004-10-22 15:50 |
Yamagata | Bus architecture optimization method for IP-based design Kyoko Ueda, Keishi Sakanushi, Noboru Yoneoka, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
In IP-based design, to find the optimal bus architecture is very important problem because bus architecture strongly aff... [more] | SIP2004-101 ICD2004-133 IE2004-77 pp.73-78 |
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