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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2005-08-19
11:10
Hokkaido HAKODATE KOKUSAI HOTEL Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo)
Threshold voltage (Vth) tuning by engineering Fermi-level pinning (FLP) on HfAlOx(N) dielectrics is demonstrated for CMO... [more] SDM2005-148 ICD2005-87
pp.31-36
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