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Committee Date Time Place Paper Title / Authors Abstract Paper #
SS, KBSE, IPSJ-SE [detail] 2023-07-20
15:15		 Hokkaido
(Primary: On-site, Secondary: Online)		 Instruction Scheduling for GPUs Utilizing Subwarp Interleaving
Junji Fukuhara, Munehiro Takimoto (TUS) SS2023-4 KBSE2023-15		 Graphics Processing Units (GPUs) exploit the Single-Instruction Multiple-Thread (SIMT) execution model, which causes bra... [more] SS2023-4 KBSE2023-15
pp.19-24
VLD 2011-03-02
13:35		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions
Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-117		 Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] VLD2010-117
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-11-30
09:50		 Fukuoka Kyushu University Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors
Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) VLD2010-65 DC2010-32		 Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is... [more] VLD2010-65 DC2010-32
pp.61-66
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] 2010-03-28
11:15		 Tokyo   Design and Evaluation of An Instruction Scheduler for FU Array Processor
Kazuhiro Yoshimura, Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2009-94 DC2009-91		 Recently, we have proposed Linear Array Pipeline Processor (LAPP) that improves energy efficiency for various workloads ... [more] CPSY2009-94 DC2009-91
pp.511-516
VLD, IPSJ-SLDM 2007-05-10
13:55		 Kyoto Kyodai Kaikan Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) 		Partial forwarding is a design method to put forwarding paths on a part of processor pipeline.
To schedule instructions... [more]		 VLD2007-2
pp.7-12
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