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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC, CPSY
(Joint)		 2011-07-28
15:15		 Kagoshima   Proposal for High Efficient DVS Using Adaptive Redundancy of FUs
Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) DC2011-15		 Recently, the well-known low power technology DVS(Dynamic Voltage Scaling) is aggressively applied to processors with Ra... [more] DC2011-15
pp.1-6
ICD 2010-12-16
15:10		 Tokyo RCAST, Univ. of Tokyo [Poster Presentation] Design of Memory Access Controller for FU Array Accelerator
Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-114		 Our previously proposed FU (functional unit) array accelerator can achieve both high energy-efficiency and binary-compat... [more] ICD2010-114
pp.95-96
ICD 2010-12-16
15:10		 Tokyo RCAST, Univ. of Tokyo [Poster Presentation] Design of An FU Network for Array Accelerators
Suguru Ooue, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-115		 We have proposed Linear Array Pipeline Processor (LAPP) as a special implementation of Function Unit (FU) array based ac... [more] ICD2010-115
pp.97-99
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] 2010-03-28
11:15		 Tokyo   Design and Evaluation of An Instruction Scheduler for FU Array Processor
Kazuhiro Yoshimura, Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2009-94 DC2009-91		 Recently, we have proposed Linear Array Pipeline Processor (LAPP) that improves energy efficiency for various workloads ... [more] CPSY2009-94 DC2009-91
pp.511-516
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