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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2012-03-07 14:35 |
Oita |
B-con Plaza |
Performance of the Evaluation of a Variable-Latency-Circuit on FPGA Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141 |
The performance of integrated circuits, which are the base of ICT nowaday,
is always requested to be improved.
In de f... [more] |
VLD2011-141 pp.127-132 |
MSS, CAS, VLD, SIP |
2011-07-01 14:30 |
Okinawa |
Okinawa-Ken-Seinen-Kaikan |
Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits Kenta Ando, Atsushi Takahashi (Osaka Univ.) CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 |
The performance of a circuit is improved by introducing error detection/correction mechanism which uses the variation of... [more] |
CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 pp.147-152 |
VLD |
2010-03-12 10:25 |
Okinawa |
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Performance evaluation of ADDER with Error-Detection-Correction Mechanism Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2009-121 |
In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum ... [more] |
VLD2009-121 pp.133-137 |
ICD |
2009-12-14 13:30 |
Shizuoka |
Shizuoka University (Hamamatsu) |
[Poster Presentation]
An evaluation of delay error rate of an adder in terms of clock period Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi (Osaka Univ.) ICD2009-91 |
Currently, digital circuits are mainly realized as synchronous circuits that uses global clocks. In clock-synchronous ci... [more] |
ICD2009-91 pp.77-81 |
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