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| Presentation | 2010-03-12 10:25 Performance evaluation of ADDER with Error-Detection-Correction Mechanism Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ)  VLD2009-121 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum delay between Flip-Flops gives a lower bound of clock period. Therefore, the reduction of the maximum delay between Flip-Flops is pursued, but it approaches the limit. In this paper, we focus on the fact that the maximum delay varies depending on the input signal pattern, and introduce an error-detection-correction mechanism that enables a circuit to work with clock period which is less than the maximum delay. In order to confirm the effect of error-detection-correction mechanism, we evaluate the delay error rate of an adder and confirm that the effective clock period of the adder is reduced by introducing error-detection-correction mechanism. \end{eabstract} |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Error-detection-correction mechanism / delay time / hold time / delay error rate / hold error rate / effective clock period / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 462, VLD2009-121, pp. 133-137, March 2010. | |
| Paper # | VLD2009-121 | |
| Date of Issue | 2010-03-03 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2009-121 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2010-03-10 - 2010-03-12 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2010-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance evaluation of ADDER with Error-Detection-Correction Mechanism |
| Sub Title (in English) | |
| Keyword(1) | Error-detection-correction mechanism |
| Keyword(2) | delay time |
| Keyword(3) | hold time |
| Keyword(4) | delay error rate |
| Keyword(5) | hold error rate |
| Keyword(6) | effective clock period |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuuta Ukon |
| 1st Author's Affiliation | Osaka University (Osaka Univ) |
| 2nd Author's Name | Masafumi Inoue |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Inst. of Tech.) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Osaka University (Osaka Univ) |
| 4th Author's Name | Kenji Taniguchi |
| 4th Author's Affiliation | Osaka University (Osaka Univ) |
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| Speaker | Author-1 |
| Date Time | 2010-03-12 10:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2009-121 |
| Volume (vol) | vol.109 |
| Number (no) | no.462 |
| Page | pp.133-137 |
| #Pages | 5 |
| Date of Issue | 2010-03-03 (VLD) |
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