| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
16:40 |
Fukuoka |
Kitakyushu International Conference Center |
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
[more] |
VLD2005-74 ICD2005-169 DC2005-51
pp.79-84 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
17:05 |
Fukuoka |
Kitakyushu International Conference Center |
Floorplan Design for 3D-VLSI
Hidenori Ohta (Tokyo Univ. of Agri. & Tech.), Toshinori Yamada (Saitama Univ.), Chikaaki Kodama, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. & Tech.) |
[more] |
VLD2005-75 ICD2005-170 DC2005-52
pp.85-90 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
09:30 |
Fukuoka |
Kitakyushu International Conference Center |
On Low Capture Power Test Generation for Scan Testing
Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST) |
High switching activity occurs when the response to a test vector is captured by flip-flops during scan testing. This ma... [more] |
VLD2005-76 ICD2005-171 DC2005-53
pp.1-6 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
09:55 |
Fukuoka |
Kitakyushu International Conference Center |
A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a broadside test generation method for
transition faults in partial scan circuits. In order to gene... [more] |
VLD2005-77 ICD2005-172 DC2005-54
pp.7-12 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
10:20 |
Fukuoka |
Kitakyushu International Conference Center |
A Note on Expansion of Convolutional Compactors on Galois Field
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
Convolutional compactors offer a promising technique of compacting test responses. In this study we expand the architect... [more] |
VLD2005-78 ICD2005-173 DC2005-55
pp.13-18 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
11:00 |
Fukuoka |
Kitakyushu International Conference Center |
Handling of Variables and Functions for Software Compatible Hardware Synthesizer CCAP
Kenichi Nishiguchi, Nagisa Ishiura, Masanari Nishimura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Nagoya Univ.), Yutetsu Takatsukasa, Manabu Kotani (Kyoto Univ.) |
We are developing a high-level synthesis tool named CCAP (C Compatible Architecture Prototyper), which synthesizes arbit... [more] |
VLD2005-79 ICD2005-174 DC2005-56
pp.19-24 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
11:25 |
Fukuoka |
Kitakyushu International Conference Center |
A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios
Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) |
In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each ta... [more] |
VLD2005-80 ICD2005-175 DC2005-57
pp.25-30 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
11:50 |
Fukuoka |
Kitakyushu International Conference Center |
no title
Kenichi Jyoko, Takahiro Ohguchi, Hirokazu Uetsu, Koji Sakai, noname, Takashi Kambe (noname) |
[more] |
VLD2005-81 ICD2005-176 DC2005-58
pp.31-36 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
13:30 |
Fukuoka |
Kitakyushu International Conference Center |
Examinations of Small-World and Scale-Free characteristics in logic circuits
Toshiaki Miyazaki (Univ. of Aizu) |
Recently, it has been reported that many networks existing in both
natural and artificial things have the Small-World ... [more] |
VLD2005-82 ICD2005-177 DC2005-59
pp.37-40 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
13:55 |
Fukuoka |
Kitakyushu International Conference Center |
Exact Minimum Factoring via Quantified Boolean Satisfiability
Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
[more] |
VLD2005-83 ICD2005-178 DC2005-60
pp.41-46 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
14:20 |
Fukuoka |
Kitakyushu International Conference Center |
An Encoding Method for Rail Outputs in LUT Cascade Emulators
Shinya Nagayasu, Tsutomu Sasao, Munehiro Matsuura (KIT) |
[more] |
VLD2005-84 ICD2005-179 DC2005-61
pp.47-52 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
14:45 |
Fukuoka |
Kitakyushu International Conference Center |
A Logic Simulation using an LUT Cascade Emulator
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) |
This paper shows a cycle-based logic simulation method using an LUT cascade emulator.
The LUT cascade emulator is an ar... [more] |
VLD2005-85 ICD2005-180 DC2005-62
pp.53-58 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
15:25 |
Fukuoka |
Kitakyushu International Conference Center |
Efficient contraction of timed signal transition graphs
Tomohiro Yoneda (NII), Chris Myers (Univ. of Utah) |
In the decomposition based synthesis method, for each output signal,
an input signal set sufficient to synthesize a cir... [more] |
VLD2005-86 ICD2005-181 DC2005-63
pp.59-64 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-02
15:50 |
Fukuoka |
Kitakyushu International Conference Center |
Structural Coverage of Traversed Transitions for Symbolic Model Checking
Xingwen Xu, Shinji Kimura (Waseda Univ.), Kazunari Horikawa, Takehiko Tsuchiya (Toshiba) |
Coverage estimation for model checking has become an important issue in practical formal verification. Transition traver... [more] |
VLD2005-87 ICD2005-182 DC2005-64
pp.65-70 |