| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| RECONF |
2006-09-14
13:00 |
Kumamoto |
Kumamoto Univ. |
Optically Reconfigurable Gate Array with manufacturing defect tolerance
Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
[more] |
RECONF2006-20
pp.1-5 |
| RECONF |
2006-09-14
13:30 |
Kumamoto |
Kumamoto Univ. |
Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays
Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
[more] |
RECONF2006-21
pp.7-11 |
| RECONF |
2006-09-14
14:00 |
Kumamoto |
Kumamoto Univ. |
An Optically Reconfigurable Gate Array with a liquid crystal hologram
Yoshiyuki Nakada, Minoru Watanabe, Fuminori Kobayashi (Kyutech) |
[more] |
RECONF2006-22
pp.13-16 |
| RECONF |
2006-09-14
14:45 |
Kumamoto |
Kumamoto Univ. |
A logic design technique using SRAM blocks
Masayuki Sato, Hiroki Wakamatsu (Ｇｔｉ) |
A low power on-board reconfigurable tester have been developed by using an FPGA. It is technically possible to configure... [more] |
RECONF2006-23
pp.17-22 |
| RECONF |
2006-09-14
15:15 |
Kumamoto |
Kumamoto Univ. |
Discussion of Memory-LSI Working as Reconfigurable Device
Masanori Yoshihara, Tetsuo Hironaka (HCU), Masayuki Sato (GTI) |
Each function included in SoC are usually tested by the built in test circuits in the chip.Testing the SoC by the built ... [more] |
RECONF2006-24
pp.23-28 |
| RECONF |
2006-09-14
15:45 |
Kumamoto |
Kumamoto Univ. |
Yield enhancement of FPGAs with intra-die variation using multiple configuration data
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
[more] |
RECONF2006-25
pp.29-34 |
| RECONF |
2006-09-14
16:30 |
Kumamoto |
Kumamoto Univ. |
[Special Invited Talk]
How to Design FPGAs in a Nanometer Process
Kazutoshi Kobayashi (Kyoto Univ.) |
This paper describes how to design an FPGA LSI using a conventional
digital-LSI design flow as a tutorial. Our researc... [more] |
RECONF2006-26
pp.35-40 |
| RECONF |
2006-09-15
09:00 |
Kumamoto |
Kumamoto Univ. |
An Implementation of Ant Colony Optimization for the MaTriX Processing Engine
Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
[more] |
RECONF2006-27
pp.1-6 |
| RECONF |
2006-09-15
09:30 |
Kumamoto |
Kumamoto Univ. |
2-dimenstional Kolmogorov-Smirnov test with PROGRAPE-4 and PGR
Akihiko Ibukiyama, Tsuyoshi Hamada, Naohito Nakasato (RIKEN), Yuichi Okuyama (Aizu Univ.) |
[more] |
RECONF2006-28
pp.7-12 |
| RECONF |
2006-09-15
10:00 |
Kumamoto |
Kumamoto Univ. |
Numerical Function Generators Based on Polynomial Approximation Suitable for FPGA Implementation
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School) |
This paper presents an architecture and a synthesis method for numerical function generators (NFGs) based on a
kth-orde... [more] |
RECONF2006-29
pp.13-18 |
| RECONF |
2006-09-15
10:45 |
Kumamoto |
Kumamoto Univ. |
Context Control Mechanism for Dynamically Reconfigurable Processor MuCCRA
Hideharu Amano, Yohei Hasegawa, Takuro Nakamura, Takashi Nishimura, Vasutan Tanbunheng (Keio Univ.) |
[more] |
RECONF2006-30
pp.19-24 |
| RECONF |
2006-09-15
11:15 |
Kumamoto |
Kumamoto Univ. |
PERFORMANCE EVALUATION OF HARDWARE MULTI-PROCESS EXECUTION ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR
Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano (Keio Univ.) |
The hardware multi-process execution is a technique to enhance throughput by dividing reconfigurable devices into severa... [more] |
RECONF2006-31
pp.25-30 |
| RECONF |
2006-09-15
11:45 |
Kumamoto |
Kumamoto Univ. |
A Parametric Study of Packet-Switched FPGA Overlay Networks
Daihan Wang, Hiroki Matsutani, Masato Yoshimi (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
The constantly upgrading gate capacity of FPGAs
enables us to implement a complex system on a chip.
A packet-switched... [more] |
RECONF2006-32
pp.31-36 |
| RECONF |
2006-09-15
13:30 |
Kumamoto |
Kumamoto Univ. |
[Special Invited Talk]
Software Radio
-- Application of Reconfigurable Devices to Wireless Communication --
Shinichiro Haruyama (Keio Univ.) |
Software radio is expected as a key technology of future wireless communication in order to realize multi-band, multi-mo... [more] |
RECONF2006-33
pp.37-42 |
| RECONF |
2006-09-15
14:45 |
Kumamoto |
Kumamoto Univ. |
Content protection system based on partial reconfiguration of FPGA
Hiroyuki Yokoyama (KDDI Labs.), Yohei Hori, Kenji Toda (AIST) |
We study the content protection system based on partial reconfiguration of FPGA. The key component is the hardware secur... [more] |
RECONF2006-34
pp.43-48 |
| RECONF |
2006-09-15
15:15 |
Kumamoto |
Kumamoto Univ. |
DESIGN OF IBM PC COMPATIBLE SYSTEM ON AN FPGA AS A PRACTICE EDUCATION
Shuhei Kinoshita, Shigeru Namiki, Naohiko Shimizu (Tokai Univ.) |
[more] |
RECONF2006-35
pp.49-54 |
| RECONF |
2006-09-15
15:45 |
Kumamoto |
Kumamoto Univ. |
Implementation of a reconfigurable Java enviroment for embedded systems
Takayuki Mori, Shinsuke Nino, YoungHun Ko, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
[more] |
RECONF2006-36
pp.55-60 |
| RECONF |
2006-09-15
16:15 |
Kumamoto |
Kumamoto Univ. |
Self Update Mechanism for Electronic Equipments with Reconfigurable FPGAs.
Kazuyuki Ushijima, Kazuo Nagata, Hideo Harada, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
[more] |
RECONF2006-37
pp.61-66 |