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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-17
09:15		 Kanagawa Hiyoshi Campus, Keio University A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures
Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-119 CPSY2007-62 RECONF2007-65		 As device feature size decreases, interconnection delay becomes the dominating factor of total delay.
In addition, as ... [more]		 VLD2007-119 CPSY2007-62 RECONF2007-65
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