Paper Abstract and Keywords |
Presentation |
2008-01-17 09:15
A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-119 CPSY2007-62 RECONF2007-65 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As device feature size decreases, interconnection delay becomes the dominating factor of total delay.
In addition, as the number of total gates and the number of wirings in each unit area increase, the number of multiplexers that is necessary for the wiring control increases.
By using a distributed-register architecture, we can synthesize circuits with register-to-register data transfer, and can reduce influence of interconnection delay.
However, as the number of wirings required for the connection between registers increases, the needed number of multiplexers is also increased.
In this paper, we propose a multiplexer reduction algorithm in high-level synthesis for distributed-register architectures.
This algorithm can reduce the number of multiplexers for each functional unit, wiring connection between local registers by optimizing a port re-assignment.
We show effectiveness of the proposed algorithm thorough experimental results. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
multiplexer / high-level synthesis / distributed-register architecture / port assignment / interconnect delay / the number of wirings / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 415, VLD2007-119, pp. 7-12, Jan. 2008. |
Paper # |
VLD2007-119 |
Date of Issue |
2008-01-10 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2007-119 CPSY2007-62 RECONF2007-65 |
Conference Information |
Committee |
RECONF CPSY VLD IPSJ-SLDM |
Conference Date |
2008-01-16 - 2008-01-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2008-01-RECONF-CPSY-VLD-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures |
Sub Title (in English) |
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Keyword(1) |
multiplexer |
Keyword(2) |
high-level synthesis |
Keyword(3) |
distributed-register architecture |
Keyword(4) |
port assignment |
Keyword(5) |
interconnect delay |
Keyword(6) |
the number of wirings |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Tetsuya Endo |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Akira Ohchi |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Nozomu Togawa |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Masao Yanagisawa |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Tatsuo Ohtsuki |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2008-01-17 09:15:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2007-119, CPSY2007-62, RECONF2007-65 |
Volume (vol) |
vol.107 |
Number (no) |
no.415(VLD), no.417(CPSY), no.419(RECONF) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2008-01-10 (VLD, CPSY, RECONF) |
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