IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-01-17 09:15
A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures
Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-119 CPSY2007-62 RECONF2007-65
Abstract (in Japanese) (See Japanese page) 
(in English) As device feature size decreases, interconnection delay becomes the dominating factor of total delay.
In addition, as the number of total gates and the number of wirings in each unit area increase, the number of multiplexers that is necessary for the wiring control increases.
By using a distributed-register architecture, we can synthesize circuits with register-to-register data transfer, and can reduce influence of interconnection delay.
However, as the number of wirings required for the connection between registers increases, the needed number of multiplexers is also increased.
In this paper, we propose a multiplexer reduction algorithm in high-level synthesis for distributed-register architectures.
This algorithm can reduce the number of multiplexers for each functional unit, wiring connection between local registers by optimizing a port re-assignment.
We show effectiveness of the proposed algorithm thorough experimental results.
Keyword (in Japanese) (See Japanese page) 
(in English) multiplexer / high-level synthesis / distributed-register architecture / port assignment / interconnect delay / the number of wirings / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 415, VLD2007-119, pp. 7-12, Jan. 2008.
Paper # VLD2007-119 
Date of Issue 2008-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-119 CPSY2007-62 RECONF2007-65

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures 
Sub Title (in English)  
Keyword(1) multiplexer  
Keyword(2) high-level synthesis  
Keyword(3) distributed-register architecture  
Keyword(4) port assignment  
Keyword(5) interconnect delay  
Keyword(6) the number of wirings  
Keyword(7)  
Keyword(8)  
1st Author's Name Tetsuya Endo  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Akira Ohchi  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Masao Yanagisawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Tatsuo Ohtsuki  
5th Author's Affiliation Waseda University (Waseda Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2008-01-17 09:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-119, CPSY2007-62, RECONF2007-65 
Volume (vol) vol.107 
Number (no) no.415(VLD), no.417(CPSY), no.419(RECONF) 
Page pp.7-12 
#Pages
Date of Issue 2008-01-10 (VLD, CPSY, RECONF) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan