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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MSS | 2015-03-06 10:25 |
Ishikawa | IT Business Plaza Musashi | Development of SMT-based model checker for assembly cords using interrupts reduction technique Junpei Kobashi, Atsushi Takeshita, Satoshi Yamane, Kohei Sakurai (Kanazawa Univ.)  MSS2014-100 |
Recently, embedded software has properties dependent on hardware (direct operation of address spaces, memory mapped I/O,... [more] | MSS2014-100 pp.53-58 |
| SS, MSS | 2014-01-31 09:55 |
Aichi | Bounded model checking based in SMT for CISC embedded assembly programs Atsushi Takeshita, Junpei Kobashi, Satoshi Yamane (Kanazawa Univ.) MSS2013-62 SS2013-59 |
In this paper,we describe the method of verification by bounded model checking based in SMT using Code Block for embedde... [more] | MSS2013-62 SS2013-59 pp.65-70 |
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| KBSE | 2012-11-22 11:25 |
Ishikawa | Kanazawa University | SMT-based Bounded Model Checking for Assembly program Junpei Kobashi, Atsushi Takeshita, Satoshi Yamane (Kanazawa Univ.) KBSE2012-41 |
In this paper, we state property verification by Bounded Model Checking using SMT solver for register level model of ass... [more] | KBSE2012-41 pp.19-24 |
| VLD, CAS, MSS, SIP | 2012-07-02 13:00 |
Kyoto | Kyoto Research Park | Verification of embedded software in Assembly code by SMT prover Atsushi Takeshita, Junpei Kobashi, Satoshi Yamane (Kanazawa Univ.) CAS2012-7 VLD2012-17 SIP2012-39 MSS2012-7 |
We propose the technique of Bounded Model Checking(BMC) for embedded assembly program. We use SMT solver for BMC. We als... [more] | CAS2012-7 VLD2012-17 SIP2012-39 MSS2012-7 pp.37-42 |
| SS, MSS | 2012-01-26 11:45 |
Kochi | Kochi City Culture-Plaza Cul-Port | A Study for Bounded Model Checking of UML State Machines Using SMT Solvers Hayato Niimura, Toshiyuki Miyamoto (Osaka Univ.) MSS2011-58 SS2011-43 |
Recently, SAT-based bounded model checking has received attention as an efficient symbolic model checking technique. It ... [more] | MSS2011-58 SS2011-43 pp.21-26 |
| SS | 2011-03-08 09:00 |
Okinawa | Okinawa-ken Seinen Kaikan | Modular Verification using Bounded Model Checking technique with Test Case Generation Yuusuke Hashimoto (Sokendai), Shin Nakajima (NII) SS2010-68 |
In bounded model checking technique, some approximation is introduced during the translation from a program to a finite ... [more] | SS2010-68 pp.91-96 |
| MSS, CAS | 2010-11-19 15:20 |
Osaka | Kansai Univ. | A Study of a Symbolic Encoding Method for Bounded Model Checking of UML State Machines with Synchronous and Asynchronous Transitions Hayato Niimura, Toshiyuki Miyamoto (Osaka Univ.) CAS2010-80 CST2010-53 |
Recently, Bounded Model Checking has received attention as a SAT-based symbolic model checking technique. The basic idea... [more] | CAS2010-80 CST2010-53 pp.83-88 |
| MSS | 2009-01-30 09:55 |
Kanagawa | Kanagawa Industrial Promotion Center | Modeling and Verification of Hybrid Systems using Boolean Differential Constraints Daisuke Ishii, Kazunori Ueda (Waseda Univ.), Hiroshi Hosobe (National Inst. of Info.) CST2008-53 |
We propose a bounded model checking method for reachability analysis of hybrid systems. In our method, a nonlinear hybri... [more] | CST2008-53 pp.67-70 |
| SS | 2008-03-03 11:25 |
Nagasaki | Nagasaki Univ. | Formal verification of multiple UML diagrams using bounded model checking Hisashi Miyazaki, Tomoyuki Yokogawa, Sadahito Sato, Yoichiro Sato, Michiyoshi Hayase (Okayama Prefectural Univ.) SS2007-60 |
In previous work, we have proposed a framework for verifying system designs by multiple UML diagrams using symbolic mode... [more] | SS2007-60 pp.19-24 |
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